搜索资源列表
ripple-lookahead-carryselect-adder
- Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedur
VHDL大作业－虞益挺036100486
- 全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
four_adder
- 应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器-Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram
vhdl
- 半加器 或门 1位二进制全加器顶层设计描述-Half adder or a binary gate full adder top-level design descr iption
adder1
- 一个全加器的VHDL程序,经过编译和仿真.-A full adder of the VHDL program, after compiling and simulation.
Electronic-Design-Automation-Vhdl
- 各种计数器，编码器，全加器等元件的VHDL语言描述-A variety of counters, encoders, such as full-adder components described in VHDL language
seven
- 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full a
Quartus7.2
- 通过VHDL实现4位全加器，8位全加器，和8位通用寄存器的设计-4-bit full adder 8-bit full adder 8-bit register using vhdl
w
- 用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.
add
- 一位全加器源码实现了MAX及其一系列器件实现全加的功能-A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian
multiplier_8_bit
- This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit)
ADDER
- 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
Desktop
- VHDL code for 16 byte ROM & n bit comparator & a full adder
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplica
add4bit
- 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
addersandsubtractors
- this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code c
Full-Adder
- 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling.z
- VHDL Code For Full Adder By Data Flow Modelling
Design-of-full-adder
- 熟悉VHDL元件例化语句的作用 熟悉全加器的工作原理 用VHDL语言设计一位二进制全加器，并仿真。-The role of components instantiated. Familiar with VHDL statements Familiar with the working principle of full adder Using VHDL language to design a binary full adder, and simulation.
full-adder
- vhdl program of full adder