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ref-sdr-sdram-verilog
- 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
cf_interleaver2
- interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器, 包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料 -interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species,
yunsuan-verilog
- 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xili
colour_light
- 一个圣诞彩灯控制芯片的vrilog源代码，可以综合，经过FPGA验证，产生四路输出，控制四路彩灯，有跑马闪，星闪等多种功能
DisplayLCD
- 基于VRILOG HDL 的LCD控制显示字符程序；
NoiseCancel1
- 噪生消除的VRILOG实现，能很好的滤出低频噪生。
trafficlight
- 次程序为用VRILOG HDL 编写的交通灯控制程序
hdl.rar
- 双向RAM控制程序,使用VRILOG HDL 编写，简单实用,DAUL RAM control
vrilog
- 包含交通灯实现等几个vrilog硬件编程的程序，基本均为老师亲自写的范本，供我们参考用的-Contains several traffic lights to achieve vrilog hardware programming procedures, teachers are personally write the basic template for our reference
key
- 键扫描 处理程序 verilog 使用时钟为50Hz // 低电平为按下,高电平为断开 // 输出状态,1为键入,0为无键-Key scanning process using the clock for Verilog 50Hz// low level for the press, high for the disconnect// output state, one for the type, 0 for no key
lcd
- lcd1602的源程序Vrilog HDL语言编写-Vrilog HDL source lcd1602 languages
adder8
- Vrilog HDL 八位加法器源程序-8 adder Vrilog HDL source
DffTech
- VRILOG硬件语言 D主控触发器DFF_MC10131源代码 -D master VRILOG hardware trigger DFF_MC10131 language source code
jiaotongdeng
- 交通灯Vrilog源代码 用于交通等灯控制 -Vrilog the source code of traffic lights for traffic lights control
we
- 多功能数字钟 多功能数字钟 Vrilog 代码-Multi-function digital clock multifunctional digital clock Vrilog code
ii
- 交通灯状态机Vrilog源代码 交通灯状态机Vrilog源代码-The traffic light state machine source code Vrilog traffic lights Vrilog state machine source code
verilog
- 里面有一百多个verilog实例 深入浅出的讲述了vrilog硬件描述语言的开发过程 成语代码以word 形式 -There are more than 100 verilog examples described in simple terms vrilog hardware descr iption language code of the development process in order to word the form of idioms
SPI_vrilog
- SPI接口源码,语言vrilog,包括MASTER和SLAVE-SPI interf for vrilog.
key
- cyclone系列下，采用计数器现实案件消抖的verilog HDL语言源码-series under the cyclone, the consumer cases Buffeting counter the reality of the verilog HDL language source code! !
add_tree_mult
- ＦＰＧＡ的ｖｒｉｌｏｇ ＨＤＬ代码，树型乘法器-FPGA-vrilog HDL code, tree multiplier