键扫描 处理程序 verilog

使用时钟为50Hz

//　　 低电平为按下,高电平为断开

//　　 输出状态,1为键入,0为无键-Key scanning process using the clock for Verilog 50Hz// low level for the press, high for the disconnect// output state, one for the type, 0 for no key