搜索资源列表
DPLLdesign
- 数字锁相环频率合成器的设计,数字鉴相器,数字滤波器,数控振荡器,反馈分频器-Digital PLL frequency synthesizer, digital phase detector, digital filter, digital control oscillator, the feedback divider
DPLL
- 模数转换的数字锁相环,代码中有详细的说明-digital phase lock loop
MB1504anjian
- 数字锁相环(MB1504)驱动程序 针对晶体 采用 12.8M 步进采用 10 KHz 的驱动程序-Digital PLL (MB1504) driver for the stepper lens used 12.8M driver using 10 KHz
PLL
- 在同步控制上,应用了“优先与抢占”的方式产生同步信号,纯硬件实现,简单可靠;使用了成熟的数字锁相环来跟踪同步信号。-A strategy of synchronization control, which combines competition coequality and priority, is mentioned in the paper and uses digital phase-lock loop to track synchronization signal
bit-sychronization
- 全数字锁相环实现位同步,通过3个触发器实现码元的边沿提取。基带码采用M序列仿真。-DPLL to achieve bit synchronization, achieved through three trigger symbol of the edge extraction. Baseband codes using M-sequence simulation.
Matlab-based-simulation-PLL-design-
- 基于Matlab仿真的数字锁相环的设计进行了详细的分析和模拟,数字和模拟锁相环的论文-Matlab-based simulation of digital PLL design, a thesis on digital and analog phase-locked loop for a detailed analysis and simulation
timer_trigger_adc_PLL
- 数字锁相环,电网同步锁相,adc采样DSP,数字锁相环,电网同步锁相,adc采样-Digital phase-locked loop, grid genlock, adc sampling DSP, digital phase-locked loop, grid genlock, adc sampling
DigLockLoop
- VHDL设计的数字锁相环,可供设计参考。-digtal lock phase loop。
VHDL-FPGA-ALL-digital-DDLL
- VHDL 全数字锁相环 ise7.1i环境实现 内有代码 和时域仿真结果-A VHDL language based on all digital phase-locked loop DPLL VHDL realization
APDLL
- 数字锁相环的FPGA设计与实现,用maxplus2实现的-DPLL FPGA design and implementation, with maxplus2 achieve
a-adpll-based-on-fpga
- FPGA实现的VHDL语言的全数字锁相环-a adpll based on fpga
Costas-matlab
- 针对扩频系统的载波同步, 研究了数字Costas 环的设计和实现方法。介绍了数字Costas 环的结构、实现 载波同步的基本方法。以二阶环为例, 分析了数字锁相环的环路滤波器的参数设计方法, 为数字Costas 环的设计提 供了参考。提出了在高速信号处理板( 以FPGA 和DSP 为基础) 中数字Costas 环的实现方案, 经工程验证, 能够实现 载波同步, 解调出所需信号。-Design and Implementation of Digital Costas-loop
cx
- 变模可逆计数器的VHDL功能描述,是数字锁相环的一个期间的程序-Reversible counter variable mode
count_zj
- 基于FPGA的数字锁相环中环路滤波器的设计-FPGA digital PLL loop filter design
pplllrarl
- 用VHDL写的数字锁相环程序源码 pll.vhd为源文文件 pllTB.vhd为testbench 可直接使用。 -Written using VHDL digital PLL pll.vhd program source code for the source text file pllTB.vhd testbench can be used directly.
FdplllzipP
- FPGA实现全数字锁相环,运用硬件描述评议议verilog HDL,顶层文件DPLL.V -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
dpll1600e
- 数字锁相环的设计,包括鉴相器,环路滤波器,spi口输出,分频器的源代码-Digital phase-locked loop design source code, including the phase detector, loop filter, spi port output divider
Programmoing
- 51单片机及其C语言程序开发实例,介绍了51单片机常用的模块电路设计与实现,主要模块有键盘、LCD显示、A/D转换、D/A转换、I2C总线应用、语音、实时时钟、红外、USB、步进电机、数字锁相环、串口通信、DDS等-51 microcontroller C language program development instance, introduced 51 single-chip module circuit design and implementation of the main mod
PLL_continious
- 数字锁相环,matlab仿真模型,用PID实现-digital PLL,MATLAB simulation module
ver3
- 全数字锁相环的verilog代码,希望能有帮助-The DPLL verilog code, hoping to help! ! !