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costas-loop
- Costas环是用来解调双边带抑制载波信号的,也是二相或四相移相键控信号解调的专用环路-Costas loop for demodulating the double sideband suppressed carrier signal, two-phase or four-phase shift keying signal demodulation dedicated loop
OFDM
- 首先根据短训练字的特性进行相关运算,进行信号到达检测,当检测到相关值大于门限一定次数后,认为有信号到达。然后根据长训练字的特性,进行相关运算,进行OFDM符号FFT窗口起始位置的估计。估计出FFT窗口的位置后,先在时域进行小频偏的估计,将两个长训练字进行小频偏补偿后,进行FFT运算,根据FFT运算的结果进行整数倍频偏的估计。这些参数估计完成后,就可以进行数据解调了。先对数据部分进行完整的频偏补偿,然后根据估计的FFT窗口位置进行FFT运算得到频域的数据,进行解调。然后在对应于导频的子载波位置上提
DCO_ST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
DPLL_TEST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
DLF
- 可增可减的计数器,可以用于全数字锁相环中的环路低通滤波器-Either upwards or downwards counter low-pass filter can be used for all-digital phase-locked loop in the loop
CalculateLoopParameters
- 环路滤波器参数计算与噪声研究(How to Calculate Loop Parameters and Phase Noise Contribution)-Loop filter parameter calculation and noise (How to Calculate Loop Parameters and Phase Noise Contribution)
renconfiguration
- 含分布式电源的配网重构遗传算法 含基因环路编码 目标为网损最小-distributed generations
sdirx
- GV7601 GSPI驱动程序 配置GV7601 支持loopback环路输出 -GV7601 GV7601 GSPI driver configuration supports loopback loop output
bank-suanfa
- 采用 VC++ 6.0 编写的 银行家 算法 的 C++实现 , 银行家算法是 操作 中 避免 因资源环路等待 造成 死锁的 方法-Prepared using VC++ 6.0 C++ bankers algorithm implementation, bankers algorithm is operating in the loop waiting for resources to avoid deadlocks methods
high-dynamic-carrier-tracking
- 基于频率锁定环路和相位锁定环路级联,高斯噪声下的高动态实现载波跟踪-Based on frequency-locked loop and a phase locked loop cascade, the Gaussian noise high dynamic carrier tracking
InputLoopThrough
- DeckLink 卡内软环路的示例代码,用于测试输入输出功能-DeckLink card soft loop sample code for testing input and output functions
test_pll
- 该源码主要实现锁相环的功能,锁相环包括输入端,鉴相器,环路滤波器,压控振荡器,以及反馈信号,我们的目的是实现输入信号和反馈信号的同步,因此,该源码描述了如何让对信号进行跟踪,捕获和锁定,最后使其输入输出同步。-The source mainly realizes the function of phase-locked loop, phase-locked loop consists of input, phase discriminator, loop filter and the volta
test_pll_1
- 该源码主要实现锁相环的功能,锁相环包括输入端,鉴相器,环路滤波器,压控振荡器,以及反馈信号,我们的目的是实现输入信号和反馈信号的同步,因此,该源码描述了如何让对信号进行跟踪,捕获和锁定,最后使其输入输出同步。-The source is mainly realize the function of phase-locked loop, phase-locked loop consists of input, phase discriminator, loop filter and the vol
Filter
- 该代码主要实现环路滤波器矩阵的设计,环路滤波器的功能主要是在鉴相器的输出端衰减高频误差分量,以提高抗干扰性能;在环路跳出锁定状态时,提高环路以短期存储,并迅速恢复信号。-The code mainly realizes the design of loop filter matrix, Loop filter function is mainly in the output of the phase discriminator attenuation of high frequency erro
usb2.0-project
- usb2.0开发的一些实例,利用端点中断进行环路测试,上位机控制LED,通过自定义请求存取外部RAM等测试工程-usb2.0 development with some examples, the use of endpoint interrupt loop test, PC control LED, through custom request access to external RAM, test engineering
buck-compensation_mathcad
- 开关电源环路设计之基于MATHCAD的buck电路的设计-Switching power supply loop design based on the buck circuit design MATHCAD
buck-mathcad-bode
- buck开关电源, 补偿环路计算程序,能够对buck的补偿环路画伯德图-buck-loop compensation calculation procedure
PLL-and-FLL-in-digital-costas-loop
- 锁相环和锁频环在数字costas环中的应用.pdf 一篇关于costa环路的新颖设计方案,包含大量的仿真图和性能分析,对学习锁相环有很大帮助-And frequency-locked loop PLL digital costas loop in the application. Pdf a novel about the costa loop design, contains a large number of simulation map and performance analysis a
tracking
- ca码的生成,还有跟踪环路的仿真,具有一定的参考价值-ca code generation, as well as tracking loop simulation, has a certain reference value
timing_GAD_16QAM
- 16QAM调制信号的GAD定时恢复,对定时恢复环路的验证和实现-Gardner Timing Recovery for 16QAM