搜索资源列表
PLLC
- 本程序利用平方环实现载波同步，使用锁相环进行跟踪相位偏移-This program makes use of the square ring to achieve carrier synchronization, with the use of PLL to track the phase shift
DesignoftrackingloopofGPSsoftwarereceiver
- 本文在分析GPS 软件接收机跟踪原理的基础上，首先比较码环与载波环不同鉴相器的性能，然后对二阶锁相环中不同环路参数设下的跟踪效果进行仿真分析，最后设计 了合适的码环与载波环路，并用实际采集的GPS 数据论证了所设计环路的有效性，为GPS 软件接收机跟踪环路的设计提供了参考。-Based on the analysis of GPS receiver tracking software on the basis of the principle, first compare the diffe
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
84f704a6df6c
- 介绍数字锁相环的基本结构,详细分析基于FPGA的数字锁相环的鉴相器、环路滤波器、压控振荡器各部分的实现方法,并给出整个数字锁相环的实现原理图。仿真结果表明,分析合理,设计正确。-MC145159 PLL frequency synthesizer design and realization of PLL frequency synthesizer the basic principles of integrated PLL chip M C 145159 work characteristic
vhdl3
- 介绍一种基于VHDL 语言的全数字锁相环实现方法， 并用这种方法在FPGA 中实现了全 数字锁相环，作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demodulation of bit synchronizatio
pll
- 用matlab模拟仿真锁相环，一个很好的程序，希望能帮到你-PLL with matlab simulation, a very good program, hope you can help
Phase-locked-loop
- 该程序是锁相环的MATLAB的简单实现程序，从中可以看到锁相环的基本功能的实现。-This program is a simple phase locked loop of MATLAB implement programs, from which you can see the basic function of phase-locked loop of implementation.
mydesign_DPLL
- 实现了数字锁相环设计，可以用于信号的时钟提取供本地时钟使用-the design introduced a method to use DPLL,we can get the local clock from the signal
a-new-digital-PLL
- 基于FPGA实现的一种新型数字锁相环设计。该设计是用VHDL来实现的，个人觉得不错，所以传上来和大家分享-FPGA-based implementation of a new digital PLL design. The design is to use VHDL to implement the individual feels good, so come and share transfer
PLL-Bible
- 本书是锁相环技术领域的经典著作，在前两版的基础上进行了大幅的改写和扩充。不仅对传统锁相技术重新进行了更深入的考察并增加了许多从未发表的新内容，反遇了近年来最新技术进展。本书的重点是讲解基本原理，同时详细介绍了频率捕获、电荷泵锁相环等热点应用问题。 本书主要适用于通信电子行业的工程技术人员以及高等院校相关专业师生。-Bible of phase locked loop technology
spll_simplest_IQ
- 利用科斯塔斯环实现软件锁相环，完成信号相位的跟踪-Costas loop using software PLL to achieve complete phase tracking signal
PLL
- 锁相环通信系统仿真 包括预处理，仿真引擎，以及后处理-PLL communication system simulation including pre-processing, simulation engines, and post-processing
并网逆变
- 单相逆变整套程序，DSP28335完成的，研究生电子竞赛全国总决赛作品，含金量极高！AD，cap，pwm，液晶显示，锁相环，等等，算法巧妙，保护完整。
sxkbc
- 应用于非理想电网环境下的单相锁相环软件设计，采用FIR滤波器进行设计。(Design of single-phase phase-locked loop software for non ideal power grid environment, using FIR filter design.)
PllTwoOrder
- Verilog编写的二阶锁相环代码，环路可以收敛。(Verilog prepared by the second-order phase-locked loop code, the loop can converge.)
verilog_PLL
- 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simula
PLL
- 通过对输入时钟进行锁相环IP核配置，产生所需的时钟信号(By configuring the input clock PLL, the IP core generates the desired clock signal)
ideal_pll
- 本程序仿真了常用的理想二阶环路，对于研究锁相环大有裨益。(This program simulates the commonly used ideal two order loop, useful for the study of phase-locked loop.)
ADF4110_4111_4112_4113
- 基于单片机的锁相环编程，锁相环可用于倍频和锁相。(PLL programming based on single chip microcomputer, PLL can be used for frequency doubling and phase locking.)
PLL_simulink
- pll锁相环simulink模型，通俗易懂，可以实现的模型(Pll phase locked loop simulink model, easy to understand, can achieve the model)