搜索资源列表
divide
- Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
dividend4
- 本设计是一个八位被除数除以四位除数，得到不超过四位的商的整数除法器。被除数、除数、商和余数都是无符号整数。-The design is an eight dividend divided by the divisor of four, to be not more than 4 business integer divider. Dividend, divisor, and remainder are unsigned integers.
fpga_div
- Altera的FPGA，设计的硬件除法器-Altera' s FPGA, the design of the hardware divider
dividers
- verilog格式的除法器，试过了，很好用，再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
Divider
- 一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl
restoring
- restoring除法器设计 经典算法了，可以仿真通过-divider restoring a classical algorithm design, simulation can be adopted
juzhenqufaqi
- 基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
chufaqichengxu
- 除法器程序，除法器模块，定点数除法的相关代码。-Divider procedures, divider module, the related fixed-point code division.
4_bit_division
- 4位除法器,文件内容为QUARTUS II支持的VHDL语言，用于做四位除法-4_bit_division
HG_chufaqi_clajiafaqi
- VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
fast_divider
- 快速除法器，采用循环移位相减算法。 已经通过仿真。-Quick divider using cyclic shift subtraction algorithm. Simulation has been passed.
division1
- 基于vhdl/verilog的18位除法器程序。已经过仿真和综合。-Based on vhdl/verilog program for 18-bit divider. Has been simulation and synthesis.
div_8
- 八位除法器 VHDL实现 八位除法器 VHDL实现-8-Bit divider 8-Bit divider 8-Bit divider
div
- 二进制除法器，采用移位相减的方法实现，位数可调-The source code of a divider
divider
- 流水型除法器，经过FPGA平台验证。宽度可以任意修改，提供计算完毕信号。-Water-type divider, after a FPGA platform validation. Width can be modified to provide the calculation is completed the signal.
divider
- 带时钟及控制的多位除法器设计，利用状态机来实现控制-multi-cycle divider design
div
- 实现了不恢复余数除法器，采用Verilog HDL编码，仿真通过。-Not to restore the balance achieved divider, using Verilog HDL coding, simulation through.
div
- VERILOG除法器，已经调试好。大家可以参照学习.-sub-divided function,I have debug it right.It is helpful to you
divider
- FPGA除法器的使用32位的，有商和余数-FPGA using 32-bit divider, there are the quotient and remainder
Dividers
- 文件中包括各种除法器，不同类型的，不同算法的。(The document includes a variety of divider, different types, different algorithms.)