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QuartusII6[1].0shiyong
- Quartus 视频教程 短短不到十分钟学会Quaruts-A short video tutorial Quartus less than 10 minutes Quaruts Society
quartus.ii.11.0-crack
- 这是最新版的quartus11.0的破解文件,怎么做我就不说了,里面说的很清楚,我已经尝试,保证能用!希望大家学习愉快! 另外此破解只做内部测试交流,切勿用于商业用途,否则后果自负,请勿广泛传播。-This is the latest version of the quartus11.0 the crack file, how do I do not say, which made it very clear, I have tried, guaranteed to last! Hope y
DDS
- 基于quartus的DDS,可以发生正弦波,方波,三角波,附带了顶层文件,注释在程序中-Quartus on the DDS, can occur sine wave, square wave, triangle wave, with the top-level documents, notes in the procedure
NIOS_TFT
- 用Quartus II 8.0(32bit),NIOS编译环境下,用TFT做的一个数码相框,附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
Crack_QII81_FULL_License
- quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
USB2.0
- usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
ALU
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
uart
- uart的vhdl实现,包含完整quartus工程文件,相信会有较大帮助-uart vhdl quartus
fpga-pwm
- 用verilog 语言写的FPGA子程序,环境是quartus II 7.2 已经在EP1C6Q240上测试过,源码包含仿真文件和仿真结果,本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
CLOCK
- 文通过ALTERA公司的quartus II软件,用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为:计时功能,24小时制计时显示;通过七段数码管动态显示时间;校时设置功能,可分别设置时、分、秒;跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
fifo-verilog
- 自己设计的一种FIFO寄存器,用verilog 编写,QUARTUS II下验证-Own design of a FIFO register, with verilog preparation, QUARTUS II certification under
UART
- 语言:verilog语言 功能:通过串口控制模块,实现FPGA与串口 通信。 仿真环境:modelsim 综合环境:quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
LVDS
- 高速串行差分接口(HSDI)设计实例,用QUARTUS和利用FPGA实现LVDS的方法。-High-speed serial differential interfaces (HSDI) design example implementation using FPGA LVDS QUARTUS and use of the method.
clk_vhdl
- Quartus II工程压缩文件,是一个典型的基于FPGA的数字钟工程项目,有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
CPU
- 一个多周期CPU的完整设计,quartus平台,Verilog实现,内含实验报告,和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写!QUARTUS II8.0平台仿真验证通过,并在硬件上运行通过测试!-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
FIR
- Quartus II中滤波器的设计,里面含有高通滤波器,低通滤波器,带阻滤波器,主要用于滤除心电信号中的干扰-Quartus II filter design, which contains a high-pass filter, low-pass filter, band stop filter, mainly used for filtering of ECG signal interference
PS_2
- 此模块用于"PS/2接口的鼠标或键盘"与"具有外部读写的8位并口单片机"双向通信模块. Verilog HDL语言编写,在Quartus II 8.1 (32-Bit)软件中编译,并下载至EPM7128SLC84-10芯片中通过. 文件中有详细的注解. 此模块具有对于PS/2时钟和数据线的滤波功能,这样减少外部干扰,保证通信的可靠性! -This module for the "PS/2 mouse or keyboard interface" and "read
horse_light4
- 六种花样的流水灯,从左至右,从右至左,中间向两边,两边向中间,跳格闪烁等。verilog语言编写; 并且扩展容易; 有两个状态机构成实现。quartus 9.0和7.1仿真通过。无错误,无警告。-Six kinds of patterns of flowing water lights, from left to right, from right to left, in the middle to both sides, both sides toward the middle, ju