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CDM2.04.16WHQLCertified
- altera quartus 9.0 在win7 64位下的下载器驱动-altera quartus 9.0 usb_byteblaster_driver in window7 64
CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
Crack_QII70
- Quartus II 7.0 crack
QII-7.2-crack
- 常用的quartus软件 7.2版本 破解文件 -Commonly used software version 7.2 crack file quartus
4
- QUARTUS 的配置及调试 flv的 -Quartus flv configuration and commissioning of the
5
- vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2
matlab_quartus
- 可以方便地将matlab里的数据导入quartus中的波形仿真文件中，很有用-Matlab can easily import the data in waveform simulation Quartus document, very useful
Quartusguide_huawei_pdf[1]
- quartus中文全部说明 可以方便初学者使用 改软件-Quartus Chinese full descr iption can be easily changed to use software for beginners
200681556499797
- 曼彻斯特编解码 用vhdl编写的，经过quartus功能仿真测试过了的-Manchester codec prepared using VHDL, the Quartus functional simulation has been tested
paobiao
- 给出了数字跑表的源代码，设计了分频模块，实现了真实的时间计数，通过这个工程的训练，能更好的了解Quartus II数字电路开发的过程。-Digital stopwatch given the source code, design the sub-frequency module, the realization of the true count of time, through this project the training, to better understand the Quart
TimeQuest_Basic
- Quartus里面的TimeQuartus资料-Quartus inside information TimeQuartus
ff
- QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。-QUARTUS II platform based on the VHDL language elevator system control procedures.
Execise
- altera官方网站上资料的示例代码Quartus II Software Design Series Foundation-altera official website information sample code Quartus II Software Design Series Foundation
Sinout
- dds正弦可控发生计全结果 用到matlab，dsp，Quartus II 6.0软件-dds controllable sinusoidal occurred wholly the result of use of matlab, dsp, Quartus II 6.0 software
vga_timing
- 此乃VGA驱动的详细源码，并配有PLL。使用Quartus II 开发。-This is a detailed source VGA driver with a PLL. Use Quartus II development.
niosIIethernetconfig
- 描述通过软核nios II在quartus环境里面实现以太网卡配置过程，。-Described through the nios II soft-core in the Quartus environment inside Ethernet card configuration process.
newvhdl
- 在 Quartus II 7.1平台下，用VLDL写的一个计时器的程序-a timer written in VLDL in Quartus II 7.1 platform
QUARTUS_II_compile_and_simulate
- Verilog HDL 在QUARTUS II下的编译和仿真顺序-Verilog HDL in QUARTUS II compiler and simulation under the order of
VGAdisplay
- VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 芯片EP2c8Q208-VHDL entry experiment. 256-color VGA display driver development software Quartus II 6.0 chip EP2c8Q208
LCD
- Quartus, Sopc Builder搭建的CPU，通过NIOS控制LCD。工程文件。-Quartus, Sopc Builder to build the CPU, through the NIOS control LCD. Engineering documents.