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Crack_QII72
- 对于quartus 7.2软件进行破解的工具保-For quartus 7.2 crack tools software security
word
- Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scroll
PLLTEST
- Altera Quartus to Pll Source
NIOS_LED
- 完整的Nios 2 演示工程，包括Quartus II 工程和NIOS IDE下的c代码。采用NIOS 2处理器控制LED。已通过实验测试。-Complete Nios 2 demonstration projects, including the Quartus II and NIOS IDE works under the c code. NIOS 2 processor to control the use of LED. Experimental tests have passed.
piano
- 电子琴，quartus开发环境，硬件连接模型，蜂鸣器-piano
miffile
- 用matlab产生mif文件。(Altera的EDA软件，如maxplus，quartus等用到的初始化rom，ram等的文件格式)-Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
quartus-reading-and-thinking
- 本资料详细介绍了quartus11的使用方法和使用quartus11进行硬件详细开发流程。-quartus11：simple using the quartus11 sofeware .
FIFO
- 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
16bit_display8bitLED
- Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. In
Leon_tutorial_Altera_english
- Leon Altera Boarsds. This shows how to synthesis leon processor to altera boards through the use of quartus 3.-Leon on Altera Boarsds. This shows how to synthesis leon processor to altera boards through the use of quartus 3.
Time
- 24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
ADC0809
- 用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
tut_nios2_introduction
- This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor a
Segment2
- ep2c5 实现 段寄存器 verilog语言，quartus 2 仿真-the realization of paragraph ep2c5 register verilog language, quartus 2 Simulation
BaseGate
- ep2c5 实现 逻辑门 verilog语言，quartus 2 仿真-ep2c5 the realization of logic gates verilog language, quartus 2 Simulation
Timer
- ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
Trafficlightscontroller
- 1， 实验题目，和实验基本要求 • • • • • • • • • • • • • • • • • • • • 2， Quartus Ⅱ的运行环境及DE2实验板简介• • • • • • 3， 电路图和线路图，电路工
quartus2
- quartus工具入门文档，altera公司官方软件翻译全文。-tool for quartus entry documents, altera company official translation of the full text of the software.
simple_verilog
- cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit
elecfans.com_quargfjc1105
- QUARTUS II的经典教程，可以快速学会QUARTUS II的一些基础应用-Tutorial QUARTUS II classic, can quickly learn to QUARTUS II of the application of some basic