搜索资源列表
Verilog-design-
- 数字逻辑基础与Verilog设计 夏宇闻版 书籍附的代码和附录文档。-The basis of digital logic with Verilog design Xia Yu Wen-print books attached code and Appendix document.
QM-algorithm
- 用于数字逻辑表达式化简的QM算法的C++实现-Simplification of logic expression——the C++ achieve of the QM algorithm
digital-logic-design-(FPGA)-based
- 夏宇闻老师的经典数字逻辑设计（基于FPGA）-Xia Wen teacher classic digital logic design (FPGA)-based
STA_plan_routing
- 关于数字逻辑设计中静态时序分析和布局布线相关的资料。-Static timing analysis in digital logic design and layout information.
microwave
- 微波炉的控制系统，数字逻辑电路实验大系统代码-Microwave oven control system, digital logic circuit experiment system code
digitalLOGIC
- 关于数字逻辑的一些简单易懂的讲解，对初学者有很好的帮助作用。-The digital logic straightforward explain good help for beginners.
Reduction
- 关于数字逻辑的化简的讲解运用的卡诺图来讲解。-To explain the use of the digital logic simplification Karnaugh map to explain.
FPGA-FIR-filter-design
- 用数字逻辑语言设计一个十六阶的FIR滤波器，通过数字电路实现滤波处理-Digital logic language design a sixteen-stage FIR filter, the filtering process is implemented by a digital circuit
Q-M
- 《数字逻辑与处理器基础》中的Q-M化简逻辑函数的算法。-QM simplifying logic functions in digital logic and processor-based algorithm.
EDA
- EDA技术与应用 数字日历电路的设计 MATLAB 数字逻辑电路-EDA technology and application
quartus
- Quartus II使用教程，Quartus II是Altera公司推出的CPLD/FPGA开发工具，Quartus II提供了完全集成且与电路结构无关的开发包环境，具有数字逻辑设计的全部特性-Quartus II using the tutorial, Quartus II Altera Corporation launched CPLD/FPGA development tool, Quartus II development kit provides a fully integrated
GreyCode
- 可求出四位格雷码的所有情况数,格雷码是数字逻辑电路中一种很有用的码，可减少可能出现的逻辑电路错误-Calculate all kinds of 4-bit Grey Code
Automatic-pencil-sharpener
- 针对自动售铅笔机的数字逻辑设计，开发工具为Quartus II 5.1。内含完整报告和可运行程序文件。可做学习参考，于君共勉。-Pencil vending machine of digital logic design, development tools for the Quartus II 5.1. Containing the full report and run the program file. Do as a reference in the king of mutual enc
Logic_Anal
- 这个程序写本来是为数字逻辑分析器读取任何文件在您的计算机和输出文本文件显示其二进制数据时序图的形式,让你看到它的逻辑状态。你也可以把它设为创建一个表的1和0组成的从左右或左边/右边,调整了数据在大端字节序或者小端字节序-This procedure was originally for digital logic analyzer to read any file in your computer and the output text file shows a timing diagram o
Verilog_HDl
- Verilog HDL是一种硬件描述语言（HDL:Hardware Discr iption Language），是一种以文本形式来描述数字系统硬件的结构和行为的语言，用它可以表示逻辑电路图、逻辑表达式，还可以表示数字逻辑系统所完成的逻辑功能。 -VHDL language is a high-level language for circuit design, digital systems primarily used to describe the structure, behavior,
EX8
- 累计进位加法器和超前进位加法器，数字逻辑课程作业-Cumulative carry lookahead adder and adder, digital logic course work
logic-design
- 数字逻辑设计,数字逻辑学习的一个好文档,提供给大家.-Digital logic design, learning a good document.
QM
- PKU 数字逻辑设计 QM算法 与大家分享，共同进步
eth
- 用数字逻辑语言描述以太网，百兆以太网MAC和MII的verilog源码-With digital logic language to describe Ethernet
logic
- 夏宇文数字逻辑设计文档，很有帮助，适合初学者，-Xia Yuwen digital logic design documents