搜索资源列表
FLL-P-locked-loop-example
- FLL+锁频环例子程序。用于实验板,用于4xx系列。-FLL+ locked loop example program. For the experimental plate for 4xx series.
carry_trk_fll1
- 此程序对BPSK调制、载波锁频跟踪进行仿真,主要目的是锁频环-sintable(k+1)=sin(2*pi*k/2^10) costable(k+1)=cos(2*pi*k/2^10)
COSTAS
- 根据韦瓦[ Weawa] 单边带调制解调法、COSTAS 锁相环及双线性变换, 提出基于软件无线电的单边带锁相解调器。解调器运行在TMS320C6203 上, 能实时处理160kHz 信号, 捕捉8kHz 频偏。-According to韦瓦[Weawa] SSB modulation and demodulation method, COSTAS PLL and the bilinear transform, based on software radio single sideband ph
YYY_DSSS
- 设计一个四用户的扩频通信系统,扩频增益为N=16,采用Walsh码进行直接序列扩频,BPSK调制,无线信道为AWGN信道。在接收端进行解扩,解调,判决,通过仿真得到其中一个用户的误比特率与信噪比的仿真结果。-Designed a four-user spread spectrum communication system, spreading gain for N = 16, using Walsh code Direct Sequence Spread Spectrum, BPSK modul
c
- wcdma里面扩频所需的0号扰码源文件,并产生S行曲线,实现超前滞后门位同步-this is GOOD!
pll_ok
- 完整的锁相环matlab代码实现,其中包括高斯噪声干扰,频差,相差,给出最后频率及相位收敛结果图。重要的是代码中有本人详细注释,易于理解-Complete phase-locked loop matlab code, including the Gaussian noise interference, frequency difference, a difference, given the final results of the frequency and phase diagram con
10-1
- MSP430系列单片机实用C语言程序设计FLL+锁频环程序-MSP430 Microcontroller utility C Programming Language FLL+-locked loop process
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一,尽管在目前大部分设计中,广泛使用芯片厂家集成的锁相环资源,如altera 的PLL,Xilinx的DLL.来进行时钟的分频,倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
Costas
- 介绍组成数字Costas环的锁相环和锁频环的应用-Describes the composition of digital Costas loop PLL and the locking ring in
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
Technologyofcarriertrackingforhighdynamicsignalsba
- 高动态给载波的跟踪带来了很大的困难,本文研究采用锁频环( FLL) 和锁相环( PLL) 相结合的方法来实现 载波跟踪-High dynamic to the carrier' s tracking has led to great difficulties, this paper uses frequency-locked loop (FLL) and phase-locked loop (PLL) methods to achieve a combination of carrie
10-1
- FLL+锁频环程序。用于实验板,用于4xx系列。-FLL+ locked loop process. For the experimental plate for 4xx series.
FLL
- 锁频环又称为自动频率控制(AFC)环,其利用反馈回路对输入频率变化进行调整,最后达到对频率的跟踪,广泛应用于雷达,卫星导航等领域对多普勒频率的跟踪。-Locked loop, also known as automatic frequency control (AFC) loop, the use of feedback loop to adjust the input frequency changes, and finally achieve frequency tracking is wi
msp430basic-routine-program-library
- 430所有基础例程程序库文件,msp430单片机内部程序源资料,可移植性强,C语言编写,包括中断嵌套程序,异步串行通信程序(空闲模式多机通信)基本定时器程序,行列式键盘,程序捕获脉冲信号周期程序,PWM输出程序,PWM输出程序,ADC12单通道和序列通道多次转换程序,FLASH擦写程序,LCD模块程序,比较器A电阻值测量程序,基本定时器程序,FLL+锁频环程序-430 all basic routines program libraries, msp430 microcontroller int
fll
- 本论文详细介绍了锁频环中的二阶环路滤波器的设计,以及进行了相应的仿真。-Of this thesis describes a second-order loop filter design in the frequency-locked loop, and the corresponding simulation.
FLL-matlab
- 用MATLAN实现了FLL(锁频环)的热噪声误差、动态应力误差、总的跟踪误差与带宽、预检积分时间等的关系图-MATLAN achieve FLL (frequency-locked loop) thermal noise error and dynamic stress error, the total tracking error and bandwidth, preflight integration time diagram
GPS-Track
- GPS卫星信号的跟踪,基于锁频环滤波器 的-GPS satellite signal tracking
PLL-and-FLL-in-digital-costas-loop
- 锁相环和锁频环在数字costas环中的应用.pdf 一篇关于costa环路的新颖设计方案,包含大量的仿真图和性能分析,对学习锁相环有很大帮助-And frequency-locked loop PLL digital costas loop in the application. Pdf a novel about the costa loop design, contains a large number of simulation map and performance analysis a
430F149-super
- 430例程大全,值得收藏 | |——3-1 调试程序 |——5-1 框架程序 |——6-1 异步串行通信程序(点对点通信) |——6-2 异步串行通信程序(地址位模式多机通信) |——6-3 异步串行通信程序(空闲模式多机通信) |——7-1 定时中断程序 |——7-2 PWM输出程序 |——7-3 捕获脉冲信号周期程序 |——7-4 软件模拟异步串行通信程序 |——7-5 基本定时器程序 |——8-
FLL
- 锁频环程序仿真,需自行选用不同的鉴频算法,例如CPAFC等-FLL-freqence lock loop simulation