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  1. chengxu

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  2. 基于动态时间规整的语音识别系统研究及其实现,用C语言编程完成-Dynamic time warping-based speech recognition system and its implementation, complete with C language programming
  3. 所属分类:Speech/Voice recognition/combine

    • 发布日期:2017-03-30
    • 文件大小:3.23kb
    • 提供者:zhanyinfang
  1. Chapter-3

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  2. Verilog数字系统设计教程(第2版)”这本书的思考题没有答案,要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:4.29kb
    • 提供者:shixiaodong
  1. Chapter-4

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  2. Verilog数字系统设计教程(第2版)”这本书的思考题没有答案,要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:7.23kb
    • 提供者:shixiaodong
  1. Chapter-5

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  2. Verilog数字系统设计教程(第2版)”这本书的思考题没有答案,要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:14.83kb
    • 提供者:shixiaodong
  1. WorROS

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  2. 具有操作系统的基本功能。能够模拟CPU以及CPU管理、模拟内存、模拟硬盘、模拟内存管理、模拟硬盘管理、模拟进程管理、模拟指令系统、模拟中断处理等,是单用户多任务操作系统。-With the operating system s basic functions. To simulate the CPU and CPU management, analog memory, analog disk, analog memory management, disk management simulatio
  3. 所属分类:OS Develop

    • 发布日期:2017-04-06
    • 文件大小:87.25kb
    • 提供者:剑心
  1. bpsk

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  2. bpsk 调制 使用的是matlab-bpsk modulation
  3. 所属分类:Communication-Mobile

    • 发布日期:2017-04-10
    • 文件大小:1.04kb
    • 提供者:hengxin wang
  1. 2DPSK

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  2. vhdl,Digital phase modulation is also known as phase shift keying, 2DPSK is binary differential phase shift keying, is a kind of digital phase modulation. Digital phase modulation using carrier phase change to transmit digital signal, usually can be
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-09
    • 文件大小:1.82mb
    • 提供者:乐逍遥
  1. Chapter-6

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  2. 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:2.91kb
    • 提供者:shixiaodong
  1. Chapter-7

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  2. 练习七在verilog hdl中使用任务(task)319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:7.35kb
    • 提供者:shixiaodong
  1. Chapter-8

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  2. 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:328.44kb
    • 提供者:shixiaodong
  1. KASIER

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  2. This a cashier program. It built in Dev C++. This program can count the total of the price s thing that you buy.-This is a cashier program. It built in Dev C++. This program can count the total of the price s thing that you buy.
  3. 所属分类:Finance-Stock software system

    • 发布日期:2017-04-13
    • 文件大小:2.28kb
    • 提供者:yuni
  1. chaiquan

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  2. 一个HGE引擎做的猜拳游戏,有兴趣的C++新手可以看看,十分简单。-HGE engine to do a finger-guessing games, are interested in C++ novice can see, very simple.
  3. 所属分类:Other Riddle games

    • 发布日期:2017-05-14
    • 文件大小:3.14mb
    • 提供者:天峰
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