资源列表
e_pro_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
pid
- 单片机C51开发，有实例有说明，是比较好的一个-C51 Microcontroller development, there are examples there are described, is a good stuff
mpeg4_RTP
- MPEG4-ES RTP Payload RTSP MPEG4 SDP
HS0038B
- 红外接收器件的使用说明，有C51的例程和说明-Infrared receiver devices for use with C51, routines and instructions
xueshengxinxiguanlixitong
- 学生信息管理系统、功能包括增加、删除、修改、查询 注册 管理员特权等功能 比较完善-Student information management system, including modify, delete, add
interpolation-filer-rtl
- synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
rs485
- RS485通讯方式的例程，测试过，是能够用的-RS485 communication routine, tested, is able to use
bayes
- 贝叶斯的分类 并用到高斯混合模型当中有很好的分类效果-bayes
asf_format
- asf 1.2 defined specifications, has been resolved in accordance with this specification part of the core code written asf, asf format of this specification is the conventional standard promulgated in 2010.
vbPsqlPserver
- vb+sql+server图书借阅管理系统 包含源程序 数据库 后台查询等功能-Book lending source database management system includes features such as background check
ReadCad
- 用ObjectARX2010开发的AUTUCAD应用，开发环境VC2008SP1，只有源代码，请自己建工程。功能：一是通过鼠标点选对象获得块属性列举；二是有一个可串行化存储，支持CArray动态数组功能的类，用于管理块属性；三是有一个操作EXCLE表格文件的类；四是画线函数中控制线宽并能显示线宽 -A AUTOCAD developer use ObjectARX2010,with VC2008SP1 enviroment Function:1 Can select a block with
LUO_TIE_CODE
- PIC16F877做的电烙铁控制器 MPLAB IDE开发环境-PIC16F877 to do soldering iron controller MPLAB IDE development environment