资源列表
danzhouqiCPU
- VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
F10-Single-Cycle-MIPS
- This a verilog code of single cycle mips-This is a verilog code of single cycle mips
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
illinoi_arm7
- 一种ARM IP core，国外一个论坛上载下来的，希望能有所用处-A ARM IP core, a forum set off abroad, and hope to be useful
fftip
- 2008-2009年优秀硕士论文之：基于FPGA的高性能32位浮点FFT IP核的开发-Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development
fir6dlms
- lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
LCD
- verilog语言编写的LCD读写代码，包括整个工程-read and write languages LCD verilog code, including the entire project
virtual_keyboard
- 通过PS2口连接键盘与FPGA，按动1-7数字键达到虚拟电子琴的效果-PS2 keyboard port connect to the FPGA ，press the number keys 1-7 to reach the effect of the virtual keyboard
POWER-48to24
- 48V转24V 100W开关电源 DC-DC-Switch to 24V 100W 48V DC-DC switching power supply
Counter
- 计数器 QuartusⅡ 10进制计数器 CLKIN为时钟输入端，CLR为清零端，Y[3..0]为四位二进制输出（BCD 码形式），CLKOUT为10进制计数器进位输出端 -Counter
VHDL
- 很详细的vhdl教程，能够帮助大家很好的学习fpga，希望能够帮助大家学习。-Vhdl tutorial is very detailed, very good to help people learn fpga, hope to help you learn