资源列表
Verilog000
- FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。-Verilog语言的学习，熟悉Verilog语言的各种语法。 ②、FPGA的学习，熟悉
duc_ddc_system_generator
- 介绍了在xilinx环境中利用system generator设计数字上变频DUC/数字下变频DDC的流程，对于初学者很有帮助-introduced the design of DUC/DDC using system generator under xilinx, it s quite helpful to fresh
tt
- 在Quartus中实现256的RAM(经过实际的应用验证).rar-Realized in the Quartus 256 RAM (after the actual application of verification). Rar
lcd_time
- 一个基于VHDL的多功能数字钟设计，能在LCD上显示时间，调整时间，整点报时，音乐为美妙的梁祝。-A VHDL-based design of multi-functional digital clock that can display time in the LCD, adjust the time, the whole point of time, music was wonderful Butterfly Lovers.
speaker
- 基于VHDL的乐曲演奏电路，完整的Quartusii编程，经测试完全成功，初学者入门好帮手，读者打开即可使用-VHDL-based music concert circuit, complete Quartusii programming, tested a total success, a good helper for beginners entry, readers can use to open
divideVerilog
- 在FPGA上编写的快速乘法器、可用于综合等模块-fast divide\
8B10BEncodeDecode
- 基于FPGA的8B10B编解码程序，内含编码和解码文件-FPGA-based 8B10B decoding process, encode and decode files containing
CompletethedirectsequencespreadspectrumsystemPNpre
- 完成直接序列扩频系统的伪码精确同步，并用FPGA进行实现-Complete the direct sequence spread spectrum system PN precise synchronization, and implementation with FPGA for
TSE
- 利用SOPC Builder搭建三速率以太网基本构架，完成以太网功能。-SOPC Builder using the basic framework set up three speed Ethernet, Ethernet function to complete.
MP3
- MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。-MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.
dds
- 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
programtested7.27
- 可综合的信道估计模块，包括解OFDM，解导频，用于8x8，2048点的OFDM信号的信道估计-Channel estimation can be integrated module, including the solution OFDM, pilot solution for the 8x8, 2048 points of OFDM signals in channel estimation