资源列表
LagInterp
- Lagrange 插值,该程序实现线性，二次，三次等等lagrange插值功能。-the interpolation of Lagrange
nilvbo
- 本文包括以下内容：逆滤波，最小二乘方滤波，顺序滤波比较等matlab代码。-This article includes the following: inverse filtering, least squares filtering, comparison of the order of filtering matlab code.
VHDL1
- 4位并行加法器，a3,a2,a1,a0,b3,b2,b1,b0,cin为输入，cout,s3,s2,s1,s0为输出-4-bit parallel adder, a3, a2, a1, a0, b3, b2, b1, b0, cin as the input, cout, s3, s2, s1, s0 as the output
subtractor4
- Verilog half subtractor module and tests build with made with gates built with expression modules.
myCLK
- 24Mhz的频率分成2Mhz的频率。 再由一个I/O口输出。-The frequency of 24Mhz into2Mhz frequency，Again by an I/O port output.
parity_check
- Parity checing program in verilog
20120924-1647
- 上位机，简单的从仪器接受程序原始内容，可供测试串口-Epistatic machine, simple from instrument accept program original content, available for testing serial port
c51
- 51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的-51 digital clock with extended assembly language
con_strech
- Contrast Strecjing of an image
RFtest
- NRF24L01 RF测试，该程序为一个载波程序。-NRF24L01 RF testing, the program is a carrier program.
SI4464_RX_TX-2
- SI4464_RX_TX-2远距离数据传输发送接收-SI4464_RX_TX-2 DEMO
soma_loka
- Sum make in vhdl code