资源列表
QuadD
- 四路D型触发器 这个例子表明一个条件任务状态能够怎样被使用来描述连续的逻辑-Quad D-Type Flip-flop This example shows how a conditional signal assignment statement could be used to describe sequential logic
IIR
- FPGA的IIR算法描述,希望对大家有用-IRR arithetics using fpga
bcd_updown_counter2
- It is a simple 4-digit bcd up down counter written in verilog
delay
- 短小易用的时序延迟程序，适用于Xilinx公司的FPGA产品-delay.vhd for Xilinx FPGA
piso.txt
- PISO implemented in VHDL.
rom_led_8
- 气短数码管的另一种驱动形式，采取代码较少。-Shortness of breath, another drive digital form
COUNTER.ZIP
- 4 bit counter example for CHDL beginners
HDB3_Code
- HDB3编码。按照HDB3规定对输入进行编码-HDB3 encoding. In accordance with the provisions of the input is encoded HDB3
lagrange
- 对原信号进行拉格朗日插值运算，实现信号重采样-The original signal Lagrange interpolation operation, to achieve signal resampling
code
- 通过对VGA 接口的显示控制设计，理解VGA 接口的时序工作原理，掌握通过计数器产 生时序控制信号的方法以及用MEGEFUNCTION 制作锁相环的方法。-Through the VGA display control interface design, understanding the timing works VGA interface, timing control method of generating control signals produced by the count
infrastructure.vhd
- infrastructure block for analog loop, vhdl, fpga, de2
D_flipflop
- D flip flop source and test bench verilog code 6