- tingchechang 停车场模拟
- 01-Comfort-Applications-in-Vehicular-Ad-Hoc-Netwo Comfort Applications in Vehicular Ad Hoc Networks Based on Fountain Coding
- shepp-logan shepp logan和sinogram 算法
- CC2530_BasicRF_Example this is very good!i like ie very much
- area_full_Matlab 利用matlab编写
- MatlabTrafficToolbox-master traffic toolbox for matlab
资源列表
12C887
- 12887shizhongde 驱动大家好好学习 网名共同进步 123456789 一定可以成功的
ADD
- ADD instruction for the HC08 Target
3d
- C语言编写的 3D立体图片生成代码,可以让你理解如何自己构建3D立体图片,还有原理.-C language, 3D three-dimensional images generated code, can let you understand how to build their own 3D three-dimensional images, as well as principle.
code_lock
- 密码锁,内部有密码的初始输入与设置密码,还有密码的鉴定.-Lock, internal code of the initial input and set the password, as well as the identification code.
uart
- 用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。-a veriog program completed on FPGA to contrlo a uart to communicaton with a computer
dac
- Delta sigma DAC for use in FPGA includes Testbench
clock
- 采用FPGA实现数字钟功能，包括调时调分整点报时等功能。-FPGA Implementation of a digital clock function, including the tune when the tune points the whole point timekeeping functions.
dac_test
- DAC_TLC5620测试模块，verilog语言-module of texting DAC_TLC5620
matlab-stereo-disparity-map
- code is matlab code that generate stereo disparity map.
3D_GO
- 3D 围棋，编写代码短，反应速度快，程序运行稳定，三维界面效果好！-3D GO, write a short code, fast response and stable operation of the program, the effect of three-dimensional interface.
vga
- FPGA board universal VGA block
equalizer
- This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.