资源列表
FIRvhdl
- 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAX
CRC16
- 用于CRC16校验的Verilog程序源代码，喜欢的拿走-Uses in CRC16 the verification the Verilog procedure source code, likes taking away
NCO
- 用verilog语言写的NCO，在quartus环境中应用-Verilog language written with NCO, quartus environment in the applications
UART
- UART verlog 源码-UART verlog.......................
4945579081DCT_2D
- dct-20 verilog vhdl de2
top_module
- OFDM Gaurd Detector, Symbol length = 1024 & Gaurad Length = 256, and test bench written in verilog!
BT656_RGB
- BT656转RGB的算法实现代码，使用VORILOG语言编写-BT656-->RGB, verilog
HAITUN
- 海豚交易系统,用于MT4各个货币对，请下载后自测，谨慎用于实盘-Dolphins trading system for MT4 each currency pair, please download self-test, caution plate for real
TCPServer
- Wince5.0 接收Socket连接。实现了Data——arrive 、Client_Connect、Client_Disconnect的事件响应(Wince5.0 receive Socket connection. The event response of Data - arrive, Client_Connect and Client_Disconnect is realized)
fft
- TMS320C6748的fft函数，源文件以及头文件(TMS320C6748's FFT function, source file, and header file)
基于DSP28335的单相PWM整流 双闭环PI控制
- 基于DSP28335的单相PWM整流 双闭环PI控制(siglephase pwm based on dsp)
DSP滤波器设计
- 这是哈尔滨工业大学数字信号处理课的课程设计作业，利用窗函数涉及滤波器分别对自己设定的测试信号和老师给定的连续频谱信号进行滤波。 我编写时先后在同一个M文件中写了很多的画图语句，如果直接F5运行，它们会互相覆盖，使用时请将需要的绘图代码复制到命令行中重新运行。(This is the course design assignment of Digital Signal Processing Course of Harbin University of Technology. The window