资源列表
FPGA-drivenLEDdisplay
- FPGA驱动LED显示:运用硬件描述语言（如VHDL）设计一个显示译码驱动器，即将要显示的字符译成8段码。由于FPGA有相当多的引脚端资源，如果显示的位数N较少，可以直接使用静态显示方式，即将每一个数码管都分别连接到不同的8个引脚线上，共需要8×N条引脚线控制.-FPGA-driven LED display: the use of hardware descr iption languages (such as VHDL) design a display decoder driver, ab
clk_div
- VHDL描述的时钟分频电路，用途广-VHDL descr iption of the clock divider circuit, uses widely ...
Lab2b
- A C example for Nios II to use the timer and to obtain the time execution performance
Windwos
- 通过concole调用windows画线函数进行画图，画10万条线并记录时间，用于比较各种画线函数的效率-Draw a line through the concole function call windows drawing, painting 100,000 lines and record the time used to compare the efficiency of a variety of drawing a line function,
MUX16
- 基于VerilogHDL的简易的16位以为累加乘法器，包括乘法器模块和测试模块，已经通过仿真测试。-Based on the simple VerilogHDL that the cumulative 16-bit multiplier, including the multiplier module and test module has been tested by simulation.
music.txt
- 在设计手动播放和自动播放可以选择使用的电路中，程序在下载完成后，可以实现手动播放和自动播放的按键转换，通过switch按键，当按键处于‘1’状态时。则处于自动播放音乐（两只老虎），当按键‘0’时，处于手动播放音乐。自动播放和手动播放互不干扰，但是可以通过按键进行转换，最终实现实验目的。-In circuit design manual play and auto play can choose to use the program after the download is complete,
lorenz_63_rihab.py
- tracer le modèle de lorenz 1963
GAH2
- 这是我收藏的一个比较高水准的matlab去隔行代码-This is my collection of a relatively high standard of matlab code deinterlacing
lab3_4
- comparing 16 point fft using 2 8-point dfts and 8 2-point dfts
RANSAC
- 随机采样一致性算法，能够从大量点云数据里提取出最优平面，而且速度较快。-RANSAC algorithm, can extract the optimal plane a large number of point cloud data, and the speed is fast.
main
- STC单片机，自己写的点阵实现心形和几个文字的程序-STC microcontroller, write their own heart-shaped lattice realization of the program and a few words
Pedometer_Cal
- 计步器的一种有效算法，只有在一定的时间内找到规律，才会记步数。-An effective algorithm of pedometer, only find law in a certain period of time, will only remember the step.