资源列表
shift_split_data
- 关于一个串行数据输入 根据时序将数据分两路输出的程序 -on a serial data input timing will be based on output data using two procedures
oc_i2c_master_v92
- I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
vga
- a code to display in VGA using VHDL lang
anti_tb
- VHDL - SUMATOR CU GENERARE TRANSP
DisplayCtrl
- LED显示，有需要的可以下载，可以实时读写数据，很方便-LED display, there is a need can be downloaded, read and write data in real time, it is convenient
qicehweideng
- 汽车尾灯控制电路的设计，正常行驶时，6个尾灯全灭，刹车时，尾灯按一定频率闪烁，左转时，左侧灯轮流闪烁，右转时，右侧的灯轮流闪烁。-Control circuit design taillights, normal driving, six taillights Quanmie, brake, tail lights flashing at a certain frequency, turn left, turn left flashing lights, turn right, the righ
radio_com_ino
- 利用串口和LUA脚本实现微软模拟飞行软件中电台的实物重建。-LUA scr ipting using serial port and physical reconstruction of Microsoft Flight Simulator software radio.
Verilog-Code-Receiver
- Verilog Code for Receiver USART
eusart
- EUSART driver for PIC18 9600,8bit-EUSART driver for PIC18
dsp
- DSP TMS320C6713访问FPGA，向FPGA寄存器中写入数据-DSP TMS320C6713 give number to FPGA
X9C103
- PIC18F6621的10K数字电位器X9C103驱动程序，亲测通过！-PIC18F6621 of 10K digital potentiometer X9C103 driver by pro-test!
fifo
- 利用stm32f407作为测试板，利用IO和精确的延时（这个延时方式任意）来模拟FIFO时序来达到和FPGA的FIFO模块进行通信。测试时用的是Altera的FPGA的FIFO模块。-Stm32f407 use as a test board, the use of IO and accurate delay (the delay in any way) to simulate FIFO timing to achieve and FPGA FIFO module to communicate.