资源列表
disp_yuv
- 我自己写的现实YUV原始数据的MATLAB程序。先进行数据的分离，再进行YUV到RGB的转换，-I wrote it myself reality YUV data of the original MATLAB. Data for the first separation and then YUV to RGB conversion.
2-10
- verilog写的2进制转换10机制代码-source for 2~10 with verilog
baudTest_TB
- baud testbenchfor sync and assync serial communication
segment
- 数码管显示，以7位二进制码对十六进制数进行编码转换-Digital tube display, with 7 bit binary code to sixteen hexadecimal encoding conversion
rxstat_widen
- takes a double-data-rate PCIe PHY interface and expands it to a double-wide single data rate interface for easier debugging
lpc11--pwm
- lcp11**下的16位定时器产生pwm波程序代码-16-bit timer generate a pwm wave code lcp11**
test12
- 自己用VerilogHDL语言编写的时钟程序，包括时钟进位计数模块，数码管显示模块和闹钟模块。在cpld芯片上经测试有效（开发环境没找到VerilogHDL，就选了VHDL，其实他们不一样的……）-Clock with Verilog HDL language written procedures, including clock binary counter module, digital display and alarm modules. The CPLD chip has been te
ds1302
- DS1302时钟芯片的初始化原始程序，在编程开发时，可以直接添加到目录下，改一下地址，就可使用。-DS1302 clock chip initialization of the original program, in the programming development, can be directly added to the directory, change it addresses, can be used.
ads1110
- I2C的AD采集ads1110，非常实用非常简单，还能达到的是14位精度-ads1110 cai ji
div
- 简单的定时器程序，可以在很多地方用到，同时不会有逻辑错误。-Simple timer program that can be used in many places, but there will be no logic errors.
car
- 循迹小车程序，通过控制左右电机的转速来达到转向循迹的目的。-Car program
vhdlqiduanshumaguandongtai
- 七段数码管显示，是动态的显示，不过后期调试还是有点问题-Seven-segment LED display, the display is dynamic, but still a little late to debug problems