资源列表
csa3
- carry save adder block3
Example-2-1
- 编译过正确的fpga开发实例，很是适合也新手入门。fpga开发新手间的交流-fpga
2
- simple code of some kind of base decoder based on verilog
Text-IO
- 基于VHDL的Testbench读取文件的编写，很有用的 基于VHDL的Testbench读取文件的编写，很有用的-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
radar_pulse
- 对雷达的分选脉冲描述字部分 的DSP程序,主要使用Ｃ语言实现的算法 -Separation of the radar pulse descr iptor part of the DSP program, the main algorithm using C language
stopwatch
- 59.59七段数码管VHDL语言编写秒表-failed to translate
truncation
- truncation using vhdl
sequential-detector
- 用状态机实现序列检测器的设计，并对其进行仿真和硬件测试-With a state machine sequence detector design, and its simulation and hardware testing
timer
- SM39R08A5 定时器程序，定时，计时，计数-SM39R08A5 timer program, timing, timing, counting
654123
- 流水灯一圈长度加1加呼吸灯 Light water lap length plus 1 plus breathing light-Light water lap length plus 1 plus breathing light
Delayms
- 各类型晶振延时函数，包括11.0592M,12M等等，想用时直接用，非常方便-Various types of crystal delay function, including 11.0592M, 12M, etc., want to direct use, very convenient
demapperSharp1(16QAM)
- This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.