资源列表
carloscomunicaciones
- rectificaciond simulation program and half-wave
analog.c
- jfwletjwevmyrejemrukrk iptyik 67koi
CLK_DIV
- verilog HDL写的时钟通用计数分频程序，设置系统时钟，并根据目标时钟，设置分频系数即可得到目标时钟。已实际测试可用。-verilog HDL write clock common procedures for the count and divide, set the system clock, and the root According to the target clock, set the frequency division factor can get the targ
uart_trs_state
- 本程序是串口的FPGA产生程序，希望在此能够给与大家共享-This program is a serial FPGA generator, I hope to give everyone shared this
donghualizi
- 是一个简单的动画。用C语言编写的。是一个计算机图形的作业。-Is a simple animation. With the C language. Is a computer graphics operation.
signal_example5_c
- C example code for signal Macros by c/c++.
base-of-51
- 在数码管上实现0——60循环显示数字，每秒加一-In the digital tube to achieve 0- 60 cycles for display numbers, plus a second
fulladder
- this is fulladder 1bit with testbench
Background-compensation
- 改程序是用MATLAB写的有关运动背景补偿的算法-Reform program is about the background motion compensation written using MATLAB algorithm
pwm
- 使用VHDL实现可调的PWM控制器，便于初学者学习-Use VHDL to achieve an adjustable PWM controller, easy for beginners to learn