资源列表
clkdiv3.v
- a program which divides the clock by 3
LED7s
- 用VHDL语言编写的 LED七段显示译码器-Written in VHDL language with the LED seven-segment display decoder
seg
- 数码管显示（verilog） 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display
adder16_2
- 16位2级流水线加法器的Verilog设计-16 2 pipeline adder Verilog Design
transpose_buffer
- verilog source code for transpose buffer 8x8 matrics
testmult_top
- TESTBENCH测试程序，小数加法器的实现，小数位设为2位，将其小数位与整数位分别显示出来。-TESTBENCH test procedures, the implementation of decimal adder, is set to two decimal places, its decimal places, respectively, with the integer-bit display.
FIR
- 10阶的F.I.R滤波器设计的 verilog代码-Verilog code for the 10-order FIR filter design
div
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-verilog multply
DistortionCorrect
- 这是用于镜头视角<pi/2的摄像头采集的图像的畸变校正。-This is used for camera Angle < PI/2 camera acquisition of image distortion correction.
main
- 本代码实现了色彩增强的算法，该算法对图像的色彩进行调节-color enhancement
SLARK-AHRS
- 云雀（SLARK)AHRS姿态解码程序,将从串口获得的数据包解码成三个姿态角-The decoding of slark AHRS from URAT port!
ram
- vhdl code for simple ram block