资源列表
binary_to_decima
- 8位全加器的VHDL描述，可用MAX+plusⅡ运行测试-8-bit full adder of the VHDL descr iption，MAX+ plus Ⅱ can be used to run test
adder8
- Vrilog HDL 八位加法器源程序-8 adder Vrilog HDL source
TS12864
- some codes for TS12864 (GLCD)
XilinxISEDesignSuite12.1
- Xilinx ISE Design Suite 12.1 cd key
univ
- universal binary counter
123
- 用此程序可实现按键对数码管的数字显示顺序控制-Can be achieved with this procedure the order of buttons on the digital control
zuoye1
- arm流水灯代码非常有用可实现六个灯轮流点亮-Rotate arm water lights the code is very useful six lights
CPU2A03
- 任天堂nes系统 cpu处理器，2a03部分代码，希望大家用得着-Nintendo nes system cpu processor 2a03 part of the code, I hope you need it
ds
- Verilog语言，实现移相,输入方波TA，输出移相后T-Phase shifted square wave TA, the phase-shifted output TAA
mux3_if_else
- implementation of multiplexer using if else statement in verilog
CHCS
- 串行测试的一个文件，是一个测试文件，可用来测试串行数据-A serial test file is a test file that can be used to test the serial data
U
- U系统算法。 简单的算出N表达式，并画出图像-U system algorithms. Simple expressions for calculating N, and draw the image