资源列表
bin2bcd
- Binary to BCD converter
t1
- 实现电机M/T法测速的VHDL代码，只要修改cnt值大小即可修改M/T法切换的频率，当小于cnt时为T法，大于时为M法。-Motor M/T method velocimetry of the VHDL code, as long as the modified value of cnt to modify the size of M/T method of frequency switching, when cnt is less than for the T method, for M gr
gexingjiegou
- 对格型滤波器进行了算法仿真，功能实现良好，我以仿真通过，请放心下载使用-Of the lattice filter algorithm for the simulation, the functional to achieve a good simulation through I, please rest assured that download
decode3to8
- Decoder3to8 in vhdl. Behavioral solution.
alu8bit
- alu 8 bit using vhdl is very useful
diivider4
- 四位除法器，写的算法布扎带，想下就下，不下也行-Four divider, with a written calculation Fabu Zha, think the next on the next, no less will do
encoder_using_if.v
- this is a verilog code of encoder using if statement.
alu
- It is 32 bit ALU code in Verilog HDL programming Language
helu
- 多路逻辑信号-数字信号转换器。可根据此文件修改输入输出口数量。- Multiplexing logic signal- digital signal converter. The number of input and output ports can be modified according to this document.
circuit_timing
- verilog延时电路的不同写法，和综合能否。可对比学习-Different wording verilog delay circuit, and comprehensive ability. Comparable learning
buffer_tri_state
- Buffer tristate in vhdl
fenpin
- 基于50M分10K 1K 1000 100 10 1的分频，占空比 10/1-Based 50M min 10K 1K 1000 100 10 1 division, duty cycle 10/100