资源列表
NTsysUnload
- 自写卸载驱动的小软件，请在VC6.0下打开学习，上传的是源码。-Write uninstall the driver from a small software, learn to open in VC6.0, upload the source code.
pll_module
- 基于verilog的 FPGA内部PLL模块设计-Based on verilog FPGA PLL design internal modules
ExampleCode_PLL_ADF4118
- ADI参考代码 内含ARM ADF4118 ADuC7026代码-ADI reference code embedded ARM ADF4118 ADuC7026 code
CLK_3DIV
- 分频模块的设计 三分频 要求占空比为50-The design of the module frequency division three points of frequency requirements than empty for 50
MyQQ1.0
- myqq程序，使用MySql数据库用协议写的myqq程序-send get request
NTsysLoad
- 自写在windows下加载驱动的小软件，在VC6.0下打开学习.-Since the write in the windows of the small load driver software, to open in VC6.0 learning.
sioad
- Example of source code SIAOD discipline
hdb3enc_rtl
- hdb3编码，实现很简单，实际验证过，可以用。-hdb3 coding to achieve is very simple, actually verified, you can use.
final
- vhdl code for given rotation
DDS
- VHDL dds信号源产生 很有查考价值-VHDL signal waveform signal generator DDS produced
wave-generator(vhdL0
- 10章 波形信号发生器 vhdl波形发生器很有学习价值-Waveform signal generator VHDL is learning value waveform generator
HardDeskInfo
- 用C++方式获得系统的硬件相关资源，用获得的相关信息可以做加密相关处理-In C++ way to get the hardware-related resources, with access to the encryption-related information processing can be done