资源列表
Digital Data Logger - MPLAB
- This is a source code for digital data logger using PIC micro-controller
9000万隐形钱刷入(yugeigei)
- 这个是征途私服*可以帮助我们做很多事情(This is a plug-in that can help us do many things)
bezier
- matlab贝叶斯算法一种，可以参考学习下(matlab bezier you can study)
multiply
- it's a simple multiplier in vhdl language
clock
- there's a clock divider for DE2 altra board clock (50MHz)
carry-look-ahead
- it's implementation for carry lookahead adder in vhdl
booth
- it's booth vhdl code for DE2 altra boards
ethernet 10-100 monitoring
- this is using mac IP core for ethernet connection in ISE xilinx for ethernet 10/100
华为_FPGA设计流程指南
- 华为_FPGA设计流程指南 FPGA设计入门教程(Huawei FPGA Design process guide)
Vivado 简明教程
- vivado简明教程 vivado入门教程 vivado简易教程(vivado API Tutorial Vivado)
华为_FPGA设计高级技巧Xilinx篇
- 华为FPGA设计高级技巧Xilinx篇 华为FPGA设计 verilog语言(HuaWei FPGA Advanced design techniques Xilinx)
Verilog典型电路设计-华为
- 华为 verilog教程 典型电路设计 verilog语言 FPGA(FPGA Typical circuit design)