资源列表
test_verilog---Copie
- a verilog-ams code for a p-a verilog-ams code for a pll
vcoPanalog_filter
- a verilog-ams code for a vco and an analog filter
Range--Kutta
- This code is able to solve an ODE problem by Range - Kutta Felming algorithm. This code is mostly applicable for Aerospace and Mechanical Engineering. Thank you
Orologio-MGT-Display_LCD_4MHz
- Library functions for KS0108. Example of Clock with PIC16F877A
fullbridgeunipolarinverter
- FULL H Bridge Unipolar inverter
fullbridgebipolarinverter
- Full H bridge bipolar inverter
cvutils-0.1.tar
- it is opencv utilities
tanchishe
- 贪吃蛇游戏，修改部分运行错误，调节了窗口等参数。-tanchisheyouxi，xiugaibufenyunxingcuowu，tiaojiele chuangkoudeng canshu。
FPGA_Project
- USB 2.0的数据传输verilog程序，采用的是slave状态机实现其功能。其中包括读、写功能 -USB 2.0 data transfer verilog program, using the slave state machine functionality. Including reading and writing functions
smb
- 前两天搞了一个用树莓派做的家庭环境监控系统，传感器ds18b20，网页显示当前温度，并且可以跳转到动态显示当前温度的网页。python和html开发，简单易懂，这个版本代码里面用的是树莓派自带的驱动。-Two days ago out of a raspberry pie made with family environment monitoring systems, sensors ds18b20, the page displays the current temperature, and
ToDoList
- 用来帮助自己合理安排工作或学习任务的一款web应用。-Reasonable arrangements to help them work or study tasks a web application.
WinerScalart
- 维纳滤波器详细的代码，对语音信号进行滤波增强，可以滤去噪音，达到使主要声音清晰的效果-Wiener filter detailed code, the speech signal enhancement filter, can filter out noise, to make clear the main sound effects