资源列表
mul_ser12
- 本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。-The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.
8bit-Shift-and-Adder--multiplier
- 8位乘法器，经移位相加算法来实现的，用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
Char5-basic-arithmetic-logic-models
- 夏宇闻著作：从算法设计到硬线逻辑的实现,CHAR5：基本运算逻辑和它们的Verilog_HDL模型-XIA Wen works: from algorithm design to hard wire logic implementation, CHAR5: basic arithmetic logic models and their Verilog_HDL
Foreign-example-of-Verilog
- 很难找到的国外经典Verilog代码例子，希望对大家有帮助-Difficult to find foreign classic Verilog code examples, we hope to help
1.VMEbus-interrupts
- VMEbus interrupts 多任务运行-VMEbus interrupts
romPlcd1602
- 用verilog hdl实现从fpga内部rom中读取数据在lcd1602上显示-The data in the fpga rom is read out and shown in lcd1602 by verilog hdl
2.Shared-memory-System-Partition
- Shared memory System Partition-2.Shared memory System Partition
manual
- it explains the basic and imporant vhdl programs. it contains SPICE programs also.
3.Shared-Semaphore
- Shared Semaphore（Multi-Processing）-Shared Semaphore
4.Shared-Memory-System-Partition
- Shared Memory System Partition
upd6464
- osd 字符叠加源码 。应用在视频监控，成熟应用 upd-osd OSD source. Used in video surveillance, mature application upd6464
TCP-socket-communication-
- Networking\TCP socket communication between two systems using socket options SO_SNDBUF and SO_RCVBUF