资源列表
Distributer
- VHDL编写的分频器。用于将50MHz的时钟脉冲分频成一个500Hz的扫描时钟和1Hz的秒脉冲。与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.A clock distributer which generates a 500Hz scaning clock and a 1Hz second impulse. It is one of my total 9 modules that are used to design a digital clock.
LM80C27
- DEVICE SPECIFICATION for Passive Matrix Color LCD Module (800 X 600 dots) Model No. LM8 O C 2 7 LM80C27.pdf
FlashTime
- 用VHDL编写。称为校时闪烁电路。一般的电子表在校时时都会使被校正的时间不停地闪烁。此模块实现了类似的功能。与我的其它8个模块配套构成一个数字钟。 -Programmed with VHDL. It is called a flashing circuit(when time is being revised).Generally, a digital watch will flash the currently revised time(for example,hour) to let t
2_5GHz_dot_sourcecode
- Frequency Counter 2,5 GHz source code
RvsTime
- 用VHDL编写。数字钟校时电路，根据表示是否校时的输入引脚、是校正小时还是校正分钟的输入引脚决定校正状态。接受一个按钮的脉冲输入，每输入一个脉冲，被校正的时间增加1.与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.The time-revising circuit of a digital clock. Detect the inputs and decide if revise time, hour or minute. It recepts an impul
ADigCLK
- 用VHDL编写的一个数字钟。该模块是顶层模块，用VHDL例化语句例化各个子模块并组装成一个完整的数字钟。与我的其它8个模块配套构成一个数字钟。 -A digital clock programmed with VHDL.This module is the top-level module, it utilizes the Component instantiation of VHDL to incorporate all submodules into a complete digital
S1_12864lcd
- 使用FPGA实现128x64lcd显示控制-control 128x64 lcd display by fpga
ddr_sdr
- ddr ram控制器，使用vhdl语言实现-ddr ram controller,designed by vhdl
decoder
- mp3译码器的实现，在fpga上实现多媒体功能-this project is the mp3 decoder， designed by vhdl
memory_cores
- 通用ram源码包，包括双口ram，单口ram，fifo等-general ram source package，include dual port ram，single port ram，fifo，etc.
ram_wb
- 宽字符ram的实现，在quartus平台实现-wide word ram，desinged by vhdl on quartus platform
a_vhd_16550_uart
- 兼容16550 uart，使用fpga实现，支持多平台-Compatible with 16550 uart, use fpga implementation, multi-platform support