资源列表
2corve224
- 天嵌科技的2440核心板规格书。 该2440核心板体积小，资资源多，价格好 是OEM的最佳选择！ ，已通过测试。 -Embedded technology 2440 core board specifications. The 2440 volume of the core board, capital resources, the price is good is the best choice for OEM , Has been tested.
Tmyethernneth
- 这是基于UCOS II操作系统，LWIP协议栈的ARM以太网接口程序，处理器是AT91SAM7x256,对于于打算学习ARM以太网接口的朋友有一定帮助，可以参考此程序实现其他硬件平台上的以太网接口的开发。 已通过测试。 -This is based on UCOS II operating system protocol stack LWIP ARM Ethernet interface program, the processor is AT91SAM7x256 have some hel
Cfat322o
- FAT32代码，开源的经典FAT32代码，我已经测试过了可用。Porting到其其他嵌入式系统，需要更改底层接口即可。如有问题，可联系bwbtmh&21cn.net -FAT32 code, open source classic FAT32 code, I have tested that can be used. Porting to other embedded systems, and can need to change the underlying interface. If y
lpc1768_UART
- lpc1768 串口编程 可用keil直接打开-lpc1768 serial programming available keil directly open
pplllrarl
- 用VHDL写的数字锁相环程序源码 pll.vhd为源文文件 pllTB.vhd为testbench 可直接使用。 -Written using VHDL digital PLL pll.vhd program source code for the source text file pllTB.vhd testbench can be used directly.
Cuniix-tsllibo
- 比较好用的触摸屏校正程序源码码，在linux -Relatively easy to use touch screen calibration procedure source code in linux
ffirr_166i
- fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 -fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.
FdplllzipP
- ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
tuxiangcaiji
- 声音信号的处理，及对信号的滤波和再恢复，matlab源码-Sound signal processing, and signal filtering and restore Matlab source
3L-npc-v-source-inverter
- an active power filter implemented with inverter
Simcom-GPRS
- SIMCOm config GPRS for new...!
led_clock
- 电子钟，可调时，初学者自制产品，保量不保质-Electronic clock, adjustable, beginner-made products, the amount shelf life