资源列表
Sim300-anhduc
- SIm300 with C++ css
VPD__using_FFe
- verilog开发一种种基于fpga的鉴相器模块 -the verilog development of all kinds based on fpga phase detector module
sfdppllli
- 简单易懂的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的的滤波有非常好的效果， 而且能参数化配置pll的级数。 已通过测试。 -Straightforward configuration VHDL code dpll. Very good results for the clock recovery phase jitter filtering, and can be parameterized configuration pll series. Has been tested.
Ts3cc2410PPLLh
- 这个是三星arm9芯片的PLLL源码，不可多的啊 -This is the Samsung arm9 chip the PLLL source can not be more
FDDDDSPLLP
- 一种基于FPGA的新的的DDS+PLL时钟发生器 -An FPGA-based new DDS+PLL clock generator
1602
- 这是大家常用到的液晶屏，1602液晶显示程序-1602 LCD display program
eeeaasy_plla
- easy pll，非常好的的PLL(锁相环设计工具)! -easy pll very good PLL (phase-locked loop design tools)
TCOLLOR_CHAR_h
- 此ip核是xvga视频接口控制器，，主要针对xilinx公司的开发工具 -This IP core is the xvga video interface controller, the main development tool for xilinx
wWinndowsCE_Si
- wince6.0 系统软件源源码一直流程处理 有详细的说明 -wince6.0 system software source code has been flow process are described in detail
s[WiinCE60]S3s
- ssamsung最近推出的3c24433的wince 6.0 bsp安装手册. -ssamsung recently launched 3c24433 wince 6.0 bsp installation manual.
IDCTTzipm
- 改进的DCT算法设计，，veriloghdl实现 -Improve the DCT algorithm design,, veriloghdl to achieve
12864DLYYP
- X5045元件资料很好的看门狗有存储功能请查收-X5045 component data good watchdog storage capabilities please find