资源列表
risc8_cpu_verilog
- 该实例设计的RSIC-CPU总线结构采用数据线（8位）和指令线（12位）独立分离的哈弗结构，把存储寄存器RAM当做寄存器来寻址使用以方便编程。-The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as
qnr_verilog
- 量化取整QNR内部主要包括一个divider模块及产生数据输出有效和循环结果到最近整数的电路，包含仿真结果图。-Rounding quantization internal QNR includes a divider module and generates data output valid and circulating the results to the nearest integer circuit, including the simulation results shown in
DCT_verilog
- DCT是数字图像处理中的一种基础算法，实现从时域到频域的转换，从而去掉时域中数据的相关性，有利于量化后对变换系数采用游程编码和Huffman编码。-DCT is a digital image processing a basic algorithm to achieve the conversion the time domain to the frequency domain, and thus remove the domain relevance of data in favor of
DES_verilog
- 用verilog实现的DES(Data Encryption Standard数据加密标准)，把64位明文输入变为64位密文输出块。-Using DES (Data Encryption Standard Data Encryption Standard) verilog to achieve, the 64 plaintext input into 64 output ciphertext block.
uart_lcd_display_XUP
- Uart串口通信程序，PC机向FPGA的串口发送数据，FPGA的串口收到数据后回传到PC机，同时显示在lcd屏。-Uart serial communication program: The serial port of PC sends data to the FPGA. After the serial port of FPGA receives the data, FPGA sends the received data back to the PC, simultaneously dis
10.-Time0-1-Mode3
- mcu 定时器例程， 主要描述timer 的功能设置-timer control
ATmega8
- 编写的AVR的硬件TWI程序，使用中断模式- Written by the AVR hardware TWI program, using the interrupt mode
3.-Watchdog
- 看门狗例程， 主要熟悉看门狗的用法,方便学习。 -watch dog program
13.-UART_Mode0
- 单片机串口的参考例程， 主要方便熟悉串口-UART PROGRAM TEST
sky_stck
- 一个强大的单片机堆栈处理函数，支持单字节、半字、字的进栈出栈，块入块出，并能形成多环形式的堆栈链。-A powerful single-chip stack handler supports single byte, half-word, word of the stack into the stack, block into the block out, and to form a multi-ring form a stack chain.
4.-Write_Erase-Flash
- 单片机flash 编写例程， 熟悉flash 的读写在MCU 下-flash write program
28.-T-Key-Scan
- 单片机touch key 的参考例程， 熟悉触摸按键的使用的实现。 -touch key program