资源列表
fifo
- 本程序实现简单的fifo传输，并没有加其他的功能，试用芯片xilinx，verilog语言编写-The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language
liushui
- 本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写-This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language
can
- stm32f10x微处理器中关于配置CAN总线的源码-mic stm32f10x.the option of can bus
MMCSD
- TMS320C674x开发板之MMC/SD操作源码，仿真器：TI XDS100V2，编译版本：7.4.4，-MMC TMS320C674x board of/SD operation source, the emulator: TI XDS100V2, compiled version: 7.4.4,
DSPLib
- TMS320C674x的DSP库，使用TMS320C674x为DSP核心的芯片/开发板均可用。-TMS320C674x DSP library, for the use TMS320C674x DSP core chip/board available.
IMGLib
- TMS320C674x的图像处理库，所有使用TMS320C674x为核心的芯片/开发板可用-TMS320C674x image processing library, all use TMS320C674x core chip/board available
MathLib
- TMS320C674x的数学函数库，所有使用TMS320C674x为核心的芯片/开发板可用-TMS320C674x math libraries, all use TMS320C674x core chip/board available
VLib
- TMS320C674x的各种*.aexxx 文件，使用TL开发板开发DSP的必备，-TMS320C674x various* .aexxx file, use the TL development board DSP development essential,
zigbee_cc2430_code
- cc2430相关程序 包含源码以及PCB设计 与ZigBee学习版视频相配套 讲解很全面-cc2430 procedures including source code and PCB Design cc2430 procedures including source code and PCB design,supporting ZigBee learning version of the video ,a very comprehensive explanation
float_add_module
- verilog编写的32位浮点数加法器。Start_Sig 和Done_Sig 是控制信号，作为启动和反馈完成，A 和B 是32 位宽的操作数输入信号，Result 则是32 位宽的输出结果。-32bits float add module use Verilog HDL.
GOIO
- coldfire单片机对于GPIO口的初始化以及配置-coldfire microcontroller GPIO port for initialization and configuration
pwm
- coldfire单片机对于PWM的初始化以及配置-coldfire microcontroller PWM port for initialization and configuration