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  1. luyinjishiyan

    0下载:
  2. 录音机实验,STM32自带的程序代码经过调试已经完全通过可以使用-Recorder experiment, STM32 comes after debugging code can be used completely by
  3. 所属分类:Other Embeded program

    • 发布日期:2017-05-09
    • 文件大小:1.64mb
    • 提供者:杨飞
  1. CC2540_spiflash

    0下载:
  2. cc2540的spi文档及例程,CC2540通过SPI读写W25Q系列flash-SPI cc2540 documents and routines, SPI read and write through the W25Q CC2540 series flash
  3. 所属分类:SCM

    • 发布日期:2017-05-05
    • 文件大小:76.17kb
    • 提供者:joneming
  1. equalizer

    0下载:
  2. This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1.23kb
    • 提供者:rion
  1. convolution

    0下载:
  2. This the code for the convolutional and the test bench for this in the verilog code.-This is the code for the convolutional and the test bench for this in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1023byte
    • 提供者:rion
  1. demapperSharp1(16QAM)

    0下载:
  2. This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:777byte
    • 提供者:rion
  1. inter_deleaver

    0下载:
  2. This the code for the interleaver and the deinterleaver in the verilog code.-This is the code for the interleaver and the deinterleaver in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.87kb
    • 提供者:rion
  1. mapperSharp1(16QAM)

    0下载:
  2. This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:697byte
    • 提供者:rion
  1. Voltage-and-current-control-

    0下载:
  2. 电压电流控制单片机程序,并显示电压电流,电子设计竞赛-Voltage and current control
  3. 所属分类:Other Embeded program

    • 发布日期:2017-05-05
    • 文件大小:37.08kb
    • 提供者:李四
  1. mt9d112_ddr2

    0下载:
  2. 镁光MT9基于FPGA图像采集模块,该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-22
    • 文件大小:37.39mb
    • 提供者:
  1. HDMI_4AV

    0下载:
  2. 该源码为基于FPGA的HDMI显示的一拖四的AV视频采集。该模块可方便移植在需要使用HDMI高清显示的场合,并且可将VGA显示一分为四,方便各个窗口显示不同的图像信息-The source for the FPGA-based HDMI display of a four of the AV video capture. The module can be easily transplanted in the need to use the HDMI high-definition displa
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-09
    • 文件大小:1.94mb
    • 提供者:
  1. HDMI_FPGA

    1下载:
  2. 该源码可基于FPGA设置多分辨率的HDMI显示,且其包含了完整的时序和端口、地址映射,可以很方便的将其移植-The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-21
    • 文件大小:5.72mb
    • 提供者:
  1. RD1213_Video_Pipeline

    0下载:
  2. This document describes the structure and implementation of a video pipeline demo design running in the Lattice ECP3-150EA-8FN1156C device based on the Sparrowhawk FX Board. This demo takes two of the four video streams DVI and SDI inputs and the
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-23
    • 文件大小:6.44mb
    • 提供者:
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