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elecfans.com-0-41-3_30
- ds 1202 pdf 资料 ds 1202 pdf -ds 1202 pdf application
max232
- ds 1202 pdf ds 1202 pdf -ds 1202 pdf ds 1202 pdf
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- TMS320C6713DSK的PCB布局图，很有用的啦-PCB layout of the TMS320C6713 DSK map you useful
Multiplier
- 4 bit multiplier written in behavioral VHDL, using logic gate logic. inputs are A and B (4 bit each) and output is C (8 bits).
CoreI2C
- CoreI2C实验的源代码-Experimental CoreI2C source code. . . . . . . . . . .
mux4x1
- mux 4x1 with 2 control inputs, written in VHDL using 3 mathods: Logic gates, if, case. the fastest model is the one implemented with the case code.
4bitMultiplier
- 4 bit multiplier implemented with behavioral VHDL code. in addition a visio shceme is attached along with a jpg copy for thoese fho dont have visio.
Ripple_Counter
- Ripple carry counter with 4 bit resolution implemented in behavioral VHDL. attaches as well is a jpg with the logic gates bock diagram. this is an asinchronous design.
Ripple_Carry_counter
- Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL.
shuzitongxinxitongjianmo01
- 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第一部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the first part of the digital communication syste
shuzitongxinxitongjianmo02
- 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第一部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the first part of the digital communication syste
telephone
- 实现长途电话，市话的计时，还有免费电话 在verilog中用状态机实现-The achievement of long-distance calls, the city of the time, then, there are toll-free number in verilog state machine used to achieve