资源列表
verilogzzhwfy
- 用Verilog实现QPSK中的差分,扰码,串并,解差分,解扰码,解串并,用MUXPLUS2进行仿真-QPSK with Verilog realize the difference, code, and serial, Xie difference, encryption codes, and solutions Series, The simulation used MUXPLUS2
VERILOGCOMP
- 设计一个字节（8 位）比较器。 要求：比较两个字节的大小，如a[7:0]大于 b[7:0]输出高电平,否则输出低电平,改写测试 模型,使其能进行比较全面的测试 。 -design a byte (8) for comparison. Requirements : To compare the size of two bytes, as a greater than [7:0] b [7:0] output margin. Otherwise, low-level output, re
VERILOGTIME
- 利用10M 的时钟，设计一个单周期的周期波形-use 10M clock, the design of a single-cycle waveform cycle
VERILOGBLOCK
- 在blocking 模块中按如下写法，仿真与综合的结果会有什么样的变化？作出仿真 波形，分析综合结果。 -in blocking module by the following wording, simulation and synthesis of the results will be what kind of changes? Make simulation waveform analysis and comprehensive results.
VERILOGSELE
- 运用always 块设计一个八路数据选择器。要求：每路输入数据与输出数据均为4 位2进制数，当选择开关(至少3 位)或输入数据发生变化时，输出数据也相应地变-always use a block design options for the Eighth Route Army data. Requirements : every road input data and output data are four two-band number, When choosing to switch (a
modelsim_userguide
- 仿真软件MODELSIM的用户使用手册，对MODELSIM用户有很大帮助。-MODELSIM simulation software users manuals, MODELSIM users to be of much help.
sdr_sdram
- 详细的SDRAM控制器HDL代码，最顶层代码，很清晰-detailed SDRAM controller HDL code top-level code, it was very clear
sdr_data_path
- SDRAM控制器Verilog员代码，数据链路模块，完成和顶层模块的数据交换-SDRAM controller member Verilog code, data link module, Top module completed and the data exchange
Params
- SDRAM控制器Verilog员代码，设计参数模块，整个模块的所有参数定义-SDRAM controller member Verilog code, design parameter module, the entire module of all parameters defined
control_interface
- SDRAM控制器Verilog员代码，控制接口模块，完成和顶层模块的控制命令的传递-SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
Commandinterface
- SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
pci_vhdl
- PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!