资源列表
pingpangqiu
- 基于basys2的简单的乒乓球小游戏，通过ise13.4开发，使用语言VHDL，能够通过VGA在显示屏显示，能够实现双人对打，有计分功能。-Simple table tennis game, based on basys2 through ise13.4 development, using VHDL language, can through the VGA display shows, can achieve a double play, scoring function.
ds769_axi_slave_burst
- xilinx AXI4 slave burst 接口的介绍文档，有助于理解IP核-The introduction of xilinx AXI4 slave into the interface documentation
RGB-to-YCbCr[Verilog]
- 基于FPGA平台的颜色色彩空间转换 RGB to YCbCr-Based on the FPGA platform color RGB to YCbCr color space transformation
msp430f5529_accelerater
- msp430f5529开发板的加速度计实验程序，可以实验加速度计，里面编写了两个简单的使用加速度计的小游戏-msp430f5529 development board accelerometer experimental procedure can experiment accelerometer, which prepared two simple little game using accelerometer
Quartus
- VERILOG AD采集程序 FIFO存储-VERILOG AD acquisition program FIFO memory
all_test_3
- FPGA芯片开发板对应器件测试程序，包括led，按键，AD/DA等多种器件-FPGA chip development board corresponding device testing procedures, including led, buttons, AD/DA and other devices
hello_sd
- 基于fpga verilog 语言和nios ii实现的spi模式下sd卡驱动，以及加入znfat文件系统的sd卡驱动，可读取sd卡内的文件。-Based on the language and under the fpga verilog realize spi mode nios ii sd card driver, and adding znfat sd card file system driver, you can read files sd card.
PCIIP-core
- 基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v” Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and write address generation and full, almost full, empty and almost empty status generatio
verilog_cordic_core
- A highly configurable 1st quadrant CORDIC core in verilog-Details Name: verilog_cordic_core Created: Sep 14, 2008 Updated: Aug 12, 2011 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other projec
axi_ad9361_tx_channel
- 采用硬件描述语言verilog进行AD9361芯片实现的代码-AD9361 using hardware descr iption languages Verilog code that chip
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
walsh
- 沃尔什函数发生器工程文件，Quartus Ⅱ 13.0版本-Walsh Function Generator