资源列表
cnt24
- VHDL24秒篮球倒计时,VHDL编写，实现23到0计数。quartues ii 9.1编写的。-VHDL24 sec basketball countdown, written in VHDL, to achieve 23 to 0 count. Quartues written in II 9.1.
THP
- THP算法的MATLAB程序，可以给初学者一个好的教学-THP algorithm MATLAB procedures, can give a good teaching beginners
DDS
- Verilog HDL实现FPGA的DDS功能，含有实验原理与代码程序-FPGA Verilog HDL realize the DDS function, principles and codes containing experimental procedures
FPGA
- FPGA中数字收发机设计，包括了编码解码，调制解调，串口收发-Digital transceiver design
PCIe_Lab(ALTERA-V5PCIe)
- 这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 -Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.
da_80m_10m
- AD9747测试Verilog测试程序,FPGA为xilinx的SP6-the test program of AD9747，FPGA IS SP6
DDS
- 可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能； 正弦波的相位可调，方波的占空比可调； -Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep The pha
UART
- 使用标准VHDL编写的RS232协议，可在CPLD或者FPGA上直接实现串口通信功能。-use VHDL to implement RS232 protocol, which can be used in CPLD or FPGA
multiplying-unit
- fpga verilog入门经典系列完整版，下载即用:乘法器-fpga verilog multiply
div
- FPGA用VHDL写的10分频程序，保证可用-FPGA using VHDL written 10 divide procedures to ensure that the available
hilbert_m
- 基于FPGA的希尔伯特变化的verilog代码-Hilbert change verilog code
uart
- 串口通信时初学FPGA者必须要掌握的基础知识，这里给出了UART通信的VHDL代码，以及仿真测试文件。-A serial port communication beginner to must master the basic knowledge of FPGA, UART communication VHDL code is given here, and the simulation test files