资源列表
BC2
- 芯片驱动控制程序，实现BC模式 B61580 1553B-B61580 1553B
RT.v
- B61580 1553B RT模式配置,芯片驱动控制程序-B61580 1553B RT
RT-ADDRESS
- 芯片驱动控制程序 61580 1553b rt-61580 1553b rt
RT-DATA
- 61580 1553b rt 芯片驱动程序 地址-61580 1553b rt address
HDMI_FPGA
- 该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植-The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted
dma_bridge_verilog
- DMA控制模块的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-DMA control module design reference, for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
AGV_1
- 修改了黑金源码的串口通讯问题，是AGV的通讯部分程序-Modify the source of black gold serial communication problem, communication is part of the program AGV
verilog
- 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyc
VDMA
- zynq7000平台上的vdma应用实例，适用于PL部分到 PS部分的高速图像传输。-vdma example on zynq7000， which is very useful to image communications between PL and PS
DIGITAL-PID
- Use verilog language design DIGITAL-PID source
20161227_sf
- AES加密算法中的列混合模块的FPGA实现源代码，采用Verillog语言，在软件Quartus II上综合-AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software
DIGITAL-SIGNAL-PROCESSING-WITH-FPGA
- 数字信号处理的FPGA实现最新版的源代码，涉及FFT变换、IIR、FIR数字滤波器等的verilog及vhdl代码-<digital signal processing with FPGA> (the latest version) . the source code involving FFT transform, IIR, FIR digital filters by verilog and vhdl.