资源列表
sha1
- 利用verilog语言实现了SHA-1机密算法，具体算法与加密芯片ds28e01一致。-Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.
DS28E01
- 用verilog语言实现加密芯片DS28E01的调用操作命令。-Using Verilog language to achieve the encryption chip DS28E01 call operation commands.
shizhong
- 这是用VHDL编写的数字逻辑时钟电路，实现计时和由23:59到00:00转换的功能，已经在FPGA中测试通过！-This is written in VHDL digital logic circuit。It can realize the function of timing and by 23:59 to 00:00 conversion, has been in the FPGA test through!
cy4ex14
- 超声波测距，包括分频模块均值滤波模块计算距离模块-verilog fpga
UVM_learning
- UVM使用指南和代码分析，有PDF学习指南文档，还有hello入门级代码供参考-UVM guides and code analysis, study guide in PDF documents, as well as entry-level code for reference hello
ReadFifo
- QuartusII 15.0版本中，在Qsys中建立的自己定制的符合Avalon总线协议的IP核，实现功能将输入的TS流识别并存储到FIFO中，Nios核再通过总线对数据进行读取-QuartusII 15 version of the Qsys in to establish their own custom Avalon bus protocol in line with the IP core, the realization of the function to enter the TS
sequence_detector
- verilog之序列检测，vivado工程，使用状态机的方式检测任意长度的数据顺序，提供四个检测工程，并全部带有Testbench,保证你能方便的学会序列检测这个知识点。-Data in a sequential manner to detect any length of sequence detection verilog, vivado engineering, using a state machine provides four detection project, and all w
PingPang_buffer_20160526
- 源码仿真 乒乓 缓存，实现数据流的传输，含有仿真测试文件，vivado工程。-Source simulation ping-pong cache data stream transmission, the file containing the simulation test, vivado project.
triplesdi
- Xilinx Triple SDI IP Sources
lms_adaptive_filter.vhd
- lms adaptive filter using desired and input stream to get the output with 4 tabs filter.
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
spi_rtl
- spi的rtl级代码设计，内含spi_slave和spi_master的行为模型-Rtl level behavioral model of spi code design, and includes spi_slave of spi_master