资源列表
TCD1304_drive
- FPGA驱动TCD1304AP线阵CCD，并经采集将数据通过串口传输至上位机-FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial
pingpong
- 用Verilog代码实现的乒乓操作，用Verilog代码实现的乒乓操作-Verilog pingpong
Cymometer
- 用FPGA设计的等精度测量频率。频率的测量范围为1Hz-100MHz。可以测占空比，测时间间隔等。可测正弦波和方波。精度大于10e（-4）-Using FPGA to design the equal precision frequency measurement.Frequency of the measuring range is 1 hz- 100 MHZ.Can examine duty ratio, time interval measurement, etc.Sine wave an
square_wave
- 利用Vivado的高层次综合实现了一个可调方波的HDL描述-use the Vivado to realize a square wave with adjustable period
ovsf
- 正交扩展稀疏码 在FPGA中实现 代码内容可靠 可以在硬件平台实现。-Sparse orthogonal spreading codes to achieve a reliable source content in FPGA can be implemented in hardware platform.
RS_Encode_Decode
- RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。-RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.
QPSK
- 这是用ISE编写的verilog语言的QPSK调制的代码-This is the QPSK modulation verilog language written with ISE code
AD9854(Altera)
- 这是个用FPGA编写的AD9854的驱动程序，它包含了FSK,PSK,ASK。-This is a written in FPGA driver of AD9854, it contains the FSK and PSK, ASK.
AX301_jtag_uart_test
- 黑金AX301开发板，jtag口驱动及调试实验代码-AX301 development board,JTAG port driver and debug experiment code
FPGA-Source-Code_VHDL
- cypress fx2lp slave fifo fpga控制端源码-source code of FX2LP_SLAVE_FIFO CONTROLLER S
LabVIEW超级玛丽
- 用LabVIEW编写超级玛丽游戏程序，可以哦学习、、
m-sequence_gen
- m序列生成verilog代码，经过仿真测试，绝对可用，带仿真说明-M sequence generated Verilog code, after the simulation test, absolutely available, with the simulation