资源列表
Uart design with application file
- user defined Baudrate with changing in run time
fir filter vhdl code
- FIR filter design using Matlab Coefficient file and RTL design for FIR filter Design
AD7606
- AD7606的状态机驱动，并口模式，verilog代码，可正常使用。-AD7606 state machine drive, verilog code, can be normal use.
latticeECP3-serdes-test-code
- lattice ECP3系列高速FPGA serdes测试代码-lattice ECP3 series high speed serdes test code
OWIRE
- OWIRE verilog代码，实现了单总线上的通信传输的HDL顶层，子模块设计和testbench内容-The code of 1wire bus
ds18b20
- 完成DS18B20单总线温度传感芯片的控制和读取，将数据16位并行传出-Complete chip DS18B20 single bus temperature sensor control and read, 16 bit parallel data coming
fft_ifft
- fft and ifft code in verilog
eth
- 基于verilog语言的以太网接口的fpga实现，用在无线通信领域，供参考-The Ethernet interface based on verilog language fpga implementation, used in the field of wireless communications, for your reference
自定义PWM IP核，符合avalon总线
- 适合初学qsys、nios者，含tb文件，仿真通过，无bug
CCD_Sim
- 用verilog HDL语言编写的面阵CCD相机输出图像程序。-The CCD camera output image process using Verilog HDL language.
fir_lms
- 基于FIR滤波器的LMS自适应算法的FPGA实现-FIR filter based on LMS adaptive algorithm on FPGA
can
- CAN总线控制器的FPGA源代码，verilog语言编写，支持CAN2.0B协议。对CAN总线开发者非常有用。-FPGA CAN bus controller source code, verilog language, support CAN2.0 protocol B. Developers of CAN bus is very useful.