资源列表
module demultiplexer1
- Verilog code for demultiplexer
Module fulladder1
- Module full adder behavioral modelling
Program of 4 to 2 Encoder
- Verilog code for encoder
Program of 2 to 4 Decoder
- Verilog code for decoder
DDS
- DDS直接数字合成器，里面包含相关的顶层文件，加法器，D触发器，mif文件(DDS direct digital synthesizer, which contains related top layer files, adder, D trigger, MIF file)
skrypt_bazydany_3temat
- Ja juz nie wiem jak mam to zweryfikowac
Guia_1B
- 0-10-0 counter to 8051 microcontroller in assembly
verilog-stopwatch-master
- verilog stop watch code for end user
DS18B20
- 利用FPGA来采集DS18B20数字温度传感器，完成测温采集的功能(The use of FPGA to collect DS18B20 digital temperature sensor to complete the function of temperature measurement and collection)
div_3
- 采用Verilog语言对时钟进行3分频，满足系统多时钟频率的要求(3 frequency division of clock in Verilog language to meet the requirement of multi clock frequency of the system)
axi_ad9361
- AXI_AD9361 的 verilog 驱动工程，包含数据接收，数据发送 AXI总线 ，全部是verliog实现(AXI_AD9361's Verilog drive project, including data reception, data transmission AXI bus, all verliog implementation)
ddr3_mig8
- fpga实现ddr数据收发测试，完整的工程，下载解压后，即可正确运行，已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)