资源列表
vivado_license_2016.4
- vivado 2016.4 license
dot_matrix
- 数码管从一到九 信息二维数组类型的分表现的装置 本店的数量越多，高分辨率支持(The digital tube is from one to nine)
spi_master
- spi通信主从模式 可以设置速率/工作模式(Master slave mode of SPI communication)
code_cover_on_black_level_test_project1
- 视频处理的黑电平校正模块的代码覆盖率测试所用的TB(The TB for the code coverage test of the video processing black level correction module)
工作簿1
- 主要关于合肥工业大学计算机方面的知识，有数据结构，计算机组成原理，java，面向对象，(Just hole teacher talk, so that six new development of the party, you find a time, with the volunteer book, together to find the blue Secretary talk, @ Wang Kuo, you're responsible for this thing, a common
cpu_vhdl_vivado
- 一个在fpga平台上的基本cpu的demo...........(A basic CPU demo on the FPGA platform...)
oneMHZ
- VHDL语言编写的20Mhz分频器，时间为1秒(20Mhz frequency divider)
spi_no_cs_13
- FPGA作为从机与STM32的全双工通信，FPGA将接收到STM32的数据返回到STM32，Modelsim仿真和板子仿真都通过(Use FPGA as slave,realize the communication between FPGA and STM32. The function has been tested is no problem.)
tx_rx_fifo
- 通过串口将接收到的数据存入fifo,fifo存满后使能串口发送功能，将接收到的数据发送出去(Use fifo to realize the receive and send function of the uart. The function is no problem.)
ad706_test
- AD7606的FPGA驱动，AD7606与FPGA通过并行模式连接。FPGA可以将AD采集到的信号转换成电压信号通过串口输出，可通过PC机串口调试助手查看。实测可用(The drive program of AD7606 write by verilog. FPGA can convert the AD7606'sigal to volatage and send the converted signal to PC through uart.)
OV7670_TFT
- 针对OV7670视频采集和加水印功能，能够在显示屏上输出摄像头的画面并在画面任意位置添加水印(OV7670 video capture and watermark function)
rdf0028
- Multiboot on Xilinx SP605