资源列表
Verilog_Ip_PLL
- 使用verilog 硬件描述语言编写的PLL调用程序，希望对大家有帮助！(Using Verilog hardware descr iption language written in the PLL call program, I hope to help you!)
A4_Key1
- 使用verilog 硬件描述语言编写的按键电路模块，希望对大家有帮助！(Using Verilog hardware descr iption language to write the key circuit module, I hope to help you!)
A4_Beep
- 使用verilog 硬件描述语言编写的蜂鸣器电路模块，希望对大家有帮助！(Using Verilog hardware descr iption language to write the key circuit module, I hope to help you!)
project_ALU
- 4-bit ALU for adding and subtracting 4 bit numbers. It displays the output on the sevensegment display
add_1p
- 用于FPGA的加法器实现程序，采用Verilog语言编写(Adder implementation program for FPGA)
add_2p
- 用于FPGA的加法器实现程序，采用Verilog语言编写，使用了两级流水线方法(Adder implementation program for FPGA)
add_3p
- 用于FPGA的加法器实现程序，采用Verilog语言编写，使用三级流水线方法(Adder implementation program for FPGA)
sda
- This is really descr iption
random
- 用简单的线性反馈移位寄存器实现了伪随机数的生成…(The pseudo random number is generated by a simple linear feedback shift register)
IIC
- IIC的程序代码，验证各国的哦哦哦哦哦哦哦哦哦哦哦哦哦哦哦(IICIICIIIC IIC program code, verify the country's Oh, oh, oh, oh, oh, oh, oh, oh, oh, oh, oh, oh oh)
ALU
- this verilog code is alu. which is perform addition and sub,mul,div
clk_div7
- 采用verilog语言，实现时钟信号的7分频(Realize the 7 frequency division of the clock signal)