资源列表
Random_creat_2017
- 产生8bit随机数，采用线性反馈移位寄存器(The 8bit random number is generated by using linear feedback shift register)
基于FPGA的彩色符号设计
- a、设计可显示横彩条和纵彩条的VGA彩条信号； b、设计可显示英语字母的VGA彩条信号； c、设计可显示移动彩色斑点的VGA彩条信号； d、设计可实现手动切换a、b、c三个功能.(The design can display VGA color color and color of the longitudinal cross signal. The design can display the VGA color signal of the English alphabet. The
introtutorial
- An example to learn how to use Quartus II
second
- 等精度测试，待测频率超过100就停止产生脉冲(Such as precision testing, more than 100 stopped produce pulse frequency under test)
Mealy_TrafficLight
- 基于FPGA交通控制器的Mealy状态机实现(Mealy state machine controller based on FPGA traffic)
systemc-2.2.0
- System C 2.2.0 developers file
新建 WinRAR ZIP 压缩文件
- 实现跨时钟域数据传输的异步fifo，和i2c总线控制器。(Asynchronous FIFO and I2C bus controller for cross clock domain data transmission.)
5.c
- ; for 16-bit app support [386Enh] woafont=dosapp.fon EGA80WOA.FON=EGA80WOA.FON EGA40WOA.FON=EGA40WOA.FON CGA80WOA.FON=CGA80WOA.FON CGA40WOA.FON=CGA40WOA.FON
uart
- 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
CPU_16bit
- 一个五段流水的16位cpu vhdl源码，可综合也可仿真(A five section of the 16 bit CPU VHDL source code, can be integrated can also be simulated)
lcd
- copy of hello word on FPGA
cic3s32
- 3阶cic滤波器，16位输出，32倍降采样处理(The 3 order CIC filter, 16 bit output, 32 fold down sampling processing)